Jun 2024: Twenty-five alumni of the Batten
Research Group gathered
for lunch in San Jose,
CA. Attendees included BS, MEng, and PhD alumni from 2010 to 2024
who are now working at Google, Apple, Qualcomm, NVIDIA, Samsung,
Tesla, Microsoft, Samaya AI, Carnegie Mellon University, and the
University of Southern California. Reconnecting with BRG alumni has
been a highlight of the sabbatical!
May 2024: Participated on a panel with
Victor Peng (President, AMD) and Tianyue Yu (Co-Founder & CTO,
Quanergy) and moderated by Subutai Ahmad (CEO, Numenta)
to discuss
the intersection of semiconductors and artificial intelligence as
part of the Cornell Silicon Valley Presents series
May 2024: Paper on a new highly scalable
open-source RISC-V manycore architecture (in collaboration with our
colleagues at Cornell University and the University of Washington)
accepted to the 51st
ACM/IEEE Int'l Symp. on Computer Architecture (ISCA'24)
May 2024: Article on the Cornell Custom
Silicon Systems (C2S2) project team published in
the Cornell
Chronicle
Apr 2024: Angela Cui received
undergraduate research funding from
the Cornell
Engineering Learning Initiatives to explore customized computer
architectures for millimeter-scale vision systems
Mar 2024: Aidan McNay was selected as a
Merrill Presidential Scholar, which is awarded to the most
outstanding graduating seniors at Cornell – Congratulations!
Jan 2024: Article on NORDTECH published in
the Cornell
Chronicle. NORDTECH is a recently funded ME Commons Technology
Hub funded through the CHIPS and Science Act which included our
exemplar research project on AI hardware.
Jan 2024: Continuing sabbatical as a
Visiting Professor in the ASIC & VLSI Research Group at NVIDIA
Jan 2024: Attended
the SLICE Lab Retreat in
Santa Cruz, CA; a wonderful way to finish the first phase of the
sabbatical
2023
Nov 2023: Derin Ozturk joined the Batten
Research Group – Welcome!
Nov 2023: Attended the RISC-V Summit in
Santa Clara, CA and the NSF CHIPS Education and Workforce Development
Convening in Washington, DC
Oct 2023: Paper on supporting a virtual
vector instruction set on a commercial compute-in-SRAM accelerator is
accepted to the 2nd
Workshop on Democratizing Domain-Specific Accelerators (WDDSA'23)
to be held in conjunction with MICRO-56
Sep 2023: Invited to present
our vision for a new
era of open-source hardware, using our work on PyMTL3 as a case
study, at the Universtat Politècnica de Catalunya (UPC) and
the Barcelona Supercomputing Center (BSC) in Barcelona, Spain
Sep 2023: Received
the Kenneth
A. Goldman '71 Teaching Award (one of the highest award for
teaching in the College of Engineering at Cornell University)
Sep 2023: Attended the DARPA Electronics
Research Initiative (ERI) summit in Seattle, WA and the Symp. on
High-Performance Chips (HOTCHIPS) at Stanford
Aug 2023:
Paper evaluating the CIFER
system-on-chip (in collaboration with our colleagues at Princeton
University) accepted for publication in IEEE Solid-State Circuits
Letters
Aug 2023: Austin Rovinski is finishing his
post-doc in the Batten Research Group and heading to be an Assistant
Professor at New York University – Congratulations!
Jul 2023: Tuan Ta successfully defended his
doctoral thesis titled "Evolutionary Hardware Specialization for
Modern Vector and Matrix Architectures". Tuan is heading to
Tenstorrent – Congratulations!
Jul 2023: Paper on new instruction set
extensions for fast, scalable, and efficient genome sequence
alignment (in collaboration with our colleagues at the Universitat
Politecnica de Catalunya and Barcelona Supercomputing Center)
accepted to the 56th
ACM/IEEE Int'l Symp. on Microarchitecture (MICRO'23)
Jul 2023: Photos from the CSL retreat
posted on the retreat
webpage
Jul 2023: Served as the selection committee
co-chair (with Jae Lee at the Seoul National University) for
the IEEE
Micro Top Picks 2023 special issue which is now published; the
issue includes some of the very best recent research in the field of
computer architecture in terms of novelty and potential for long-term
impact.
Jul 2023: The ECE
5745 testchips came back; the
chip was fabricated on SkyWater 130nm through the efabless ChipIgnite
program. The chip included four projects with 15 students
participating: a CRC32 checksum unit, a latency insensitive
synthesizable memory, a 2x2 systolic array multiplier, and a greatest
common divisor unit.
Jun 2023: Research group attended the 50th
ACM/IEEE Int'l Symp. on Computer Architecture (ISCA'23) in Orlando, FL
including a chance to catch up with BRG alumni Christopher Torng and
Derek Lockhart
Jun 2023: The
student-led Cornell
Custom Silicon Systems (C2S2) project team successfully taped out
two chips on SkyWater 130nm through the efabless ChipIgnite program;
an analog test chip includes two variants of a full-custom op-amp and
a separate digital test chip includes a 32-point fast Fourier
transform with corresponding SPI interfaces to read input data from a
microphone and output the corresponding frequency-domain signal.
May 2023:
Attended MemPanG23,
a hands-on course on computational pangenomics held at the University
of Tennessee Health Science Center in Memphis, TN
May 2023: Anya Prabowo, Bryce Roth, Dhruv
Sharma, and Megha Shyam completed their MEng design projects and
graduated. Anya is heading to NVIDIA; Bryce is heading to Miter, and
Megha is heading to Apple – Congratulations!
May 2023: Co-organized
the Computer Systems
Laboratory Retreat at the Moakley House with over 60 attendees,
two distinguished keynote speakers, an alumni panel, student research
talks, and a poster session
Mar 2023: Invited to present work
on PyMTL3 at NVIDIA
research
Mar 2023: Courtney Golden was selected as a
Merrill Presidential Scholar, which is awarded to the most
outstanding graduating seniors at Cornell, and also earned a National
Science Foundation (NSF) Graduate Research Fellowship –
Congratulations!
Jan 2023:
Paper evaluating the CIFER
system-on-chip (in collaboration with our colleagues at Princeton
University) accepted for publication in
the IEEE Custom Integrated
Circuits Conf. (CICC'23); CIFER is a 4x4mm 456M-transistor chip
in GlobalFoundries 12nm which includes four RISC-V RV64GC Ariane
cores (implemented using SystemVerilog), 18 RISC-V RV32IM tiny cores
(implemented using PyMTL3), and an embedded FPGA (implemented using
PRGA) interconnected through a heterogeneous cache coherent memory
system.
Dec 2022: Jack Brzozowski, Kyle Infantino,
Dilan Lakhani, Angela Zou, and Lauren Shen completed their MEng
design projects and graduated. Jack is heading to AMD; Kyle, Dilan,
and Lauren are heading to Apple; and Angela is heading to Qualcomm
– Congratulations!
Dec 2022: Co-advising the brand
new Cornell Custom
Silicon Systems (C2S2) project team. C2S2 is a student-led team
of 25 diverse students including sophomores, juniors, and seniors
organized into six subteams focusing on digital design and
verification, analog design, software, system architecture, and
project management. C2S2 is working hard towards their first tapeout
on SkyWater 130nm this spring!
Dec 2022: Article on Jack Brozozowski, Kyle
Infantino, and Dilan Lakhani's MEng design project which involved
designing, testing, fabricating, and testing a custom RISC-V
microcontroller in TSMC 180nm published as an
ECE
spotlight news item
Nov 2022: Organized a hands-on activity for
20 freshmen to introduce them to computer engineering
by building
an Internet-of-things motion-detector plus alarm system as part of
the educational outreach initiatives funded through a National
Science Foundation (NSF) research grant
Oct 2022: Khalid Al-Hawaj successfully
defended his doctoral thesis
titled "Ephemeral Vector
Engines". Khalid will be starting as an Assistant Professor at
King Fahd University (KFUPM) – Congratulations!
Aug 2022: Invited to attend the virtual
Google Accelerators, Compute, Reliability, Security Workshop to
discuss research problems facing Google in the areas of computer
systems
Jul 2022: Co-taught (with Adrian Sampson) a
week-long computer systems hardware module for
Cornell's Rising
Sophomore Summer Program in Computer Science (CSMore) partially
funded through the broader impact plan of our NSF Panorama grant.
Students learned about digital logic, computer arithmetic, and simple
processors through a series of lectures, in-class activities, and
labs. By end of the week, students had incrementally developed a
"Femto-Processor" from just basic logic gates in Logisim. The
Femto-Processor supported two instructions (i.e., write immediate and
add) and was capable of executing up to 16-instruction programs to do
simple arithmetic and generate the Fibonacci sequence.
Jul 2022: Organized a special session for
the 59th ACM/IEEE Design Automation Conf. (DAC'22) on
breaking down physical design barriers with open and agile flow
tools; the session was chaired by Megan Wachs (SiFive) and included
talks by Bora Nikolic (UC Berkeley)
on Hammer,
Christopher Torng (Stanford/USC)
on mflowgen,
and Andreas Olofsson (Zero ASIC)
on silicon
compiler with over 50 attendees
Jun 2022 Participated in the
NYDesign/efabless IC design workshop in Rome, NY to discuss the
emerging open-source hardware design ecosystem in upstate New York
Jun 2022: Taped out
first teaching test chip for
ECE 5745 Complex
Digital ASIC Design on SkyWater 130nm through the efabless
ChipIgnite program. The chip included four projects with 15 students
participating: a CRC32 checksum unit implemented using C++ high-level
synthesis via Mentor CatapultC, a latency insensitive synthesizable
memory implemented in PyMTL3, a 2x2 systolic array multiplier
implemented in SystemVerilog, and a greatest common divisor unit
implemented in SystemVerilog. Each unit included its own dedicated
SPI interface for isolated testing.
Jun 2022:Research group attended the
49th ACM/IEEE Int'l Symp. on Computer Architecture (ISCA'22) in New
York City, NY
Jun 2022: BRG alumnus Christopher Torng
will be starting as an Assistant Professor in the Department of
Electrical and Computer Engineering at the University of Southern
California in January 2023
Jun 2022: Attended the final DARPA
IDEA/POSH wrap-up meeting in San Diego, CA (with our collaborator
Prof. David Wentzlaff at Princeton University) where we presented
program outcomes on open-source cache coherent memory systems,
open-source synthesizable FPGA generators, open-source on-chip
network generators, open-source RTL testing frameworks, and a recent
test chip in GlobalFoundries 14nm that served to silicon validate
this open-source IP
May 2022: Our hint to enable more advanced
JIT optimizations in PyPy, which was featured in
our CGO'20 paper on
type freezing,
was merged
upstream thanks to the hard work of Lin Cheng and our
collaborator Carl Friedrich Bolz-Tereick
May 2022: Lakshmi Bolla completed her MEng
design project and graduated. Lakshmi is heading to Qualcomm –
Congratulations!
May 2022: Taped out BRGTC5, our fifth
computer architecture test chip: a 2x2.5mm chip in TSMC 180nm
designed and implemented using PyMTL3 by Jack Brozozowski, Kyle
Infantino, and Dilan Lakhani
(block
diagram, die photo). The
chip includes a RISC-V TinyRV2 five-stage pipelined microcontroller
with a 16KB instruction memory, 16KB data memory, 4–8 digital
I/Os and a SPI master interface to enable attaching peripherals,
low-power sleep mode which wakes up on a digital input, and an SPI
minion interface to enable a host computer to test the chip and load
programs. The chip used a sophisticated PyMTL3-based pre- and
post-silicon testing strategy.
Mar 2022: Austin Rovinski from the
University of Michigan joined the Batten Research Group as a
Postdoctoral Associate – Welcome!
Feb 2022: Invited to serve as the co-chair
(with Jae Lee at the Seoul National University) for the IEEE Micro
Top Picks 2023 selection committee (plenty of lead time to prepare!)
Nov 2021: Article on our NSF Panorama
project to explore integrated rack-scale acceleration for
computational pangenomics published in
the Cornell
Chronicle (shorter article)
and Cornell
ECE News (longer article)
Oct 2021: Defense Advanced Research
Projects Agency (DARPA) proposal to explore realistic nanophotonic
system implementation (with our collaborators Al Molnar at Cornell
and Keren Bergman at Columbia) is funded through Intel as part of
various DARPA programs on both heterogeneous integration and photonic
communication
Oct 2021: Paper on
a tensor
processing framework for CPU-manycore heterogeneous systems (in
collaboration with our colleagues at Cornell and the University of
Washington) accepted for publication in IEEE Transactions on
Computer-Aided Design of Integrated Circuits and Systems (TCAD)
Sep 2021: Invited to serve on the program
committee for the IEEE Micro Top Picks 2022 special issue
Sep 2021: National Science Foundation (NSF)
proposal
to explore
integrated rack-scale acceleration for computational pangenomics
(with our collaborators Prof. Zhiru Zhang, Adrian Sampson, and Ed Suh
at Cornell University, Prof. Michael Taylor at the University of
Washington, and Prof. Pjor Prins and Erik Garrison at the University
of Tennessee Health-Science Center) is funded as part of the NSF
Principles and Practice of Scalable Systems (PPoSS) program
Aug 2021: Article on this year's CURIE
Academy published in
the Cornell
Chronicle
Aug 2021: Group of undergraduates, led by
Cameron Haire and also including Rohan Agarwal, Kenneth Mao, and Ken
Ho successfully tested their TSMC 180nm tapeout using
an "at-home COVID-safe" chip
testing setup which included a DC power supply, Analog Discovery
2 logic analyzer & pattern generator, USB-to-SPI adapter, and
various other electronics prototyping equipment
Jul 2021:
Invited to serve on the national selection committee for the
Churchill
Scholarship
Jul 2021: Directed the week-long design
experience for CURIE Academy 2021
entitled "Computing at
the Edge" as part of the educational outreach initiatives funded
through a recent National Science Foundation (NSF) grant
Jul 2021: Article on preparations for this
year's CURIE Academy which will enable high-school girls to design,
build, and test Internet-of-Things devices published
in Cornell
ECE News
May 2021: Group of undergraduates,
including Rohan Agarwal, Kenneth Mao, Cameron Haire, Ken Ho, and
Angela Zou, taped out BRGTC3 and BRGTC4, our third and fourth
computer architecture test chips. BRGTC3 had a hold-time violation
(valuable learning experience!). BRGTC4 is a 2x2.5mm chip in TSMC
180nm and includes an SPI interface, UC Berkeley floating-point
multiply-add unit, and a standard-cell-based digital clock generator
and will lay the foundation for more undergraduate-led research test
chips
May 2021: Invited to present
our vision for
a new era of open-source system-on-chip design, using our work on
PyMTL3 and Celerity as case studies, at the Hardware Systems
Collective Seminar at the University of California, Santa Cruz, CA
May 2021: Rohan Agarwal and Kenneth Mao
completed their MEng design project and graduated. Both Rohan and
Kenneth are heading to Apple – Congratulations!
May 2021: Presented our work on designing
accelerator-centric system-on-chips using heterogeneous cache
coherence and served on two panels discussing HDLs and emerging
technologies at the ADA SRC JUMP center annual symposium
May 2021: Moyang Wang, Shunning Jiang, and
Tuan Ta prepared
a demonstration video
discussing on our ongoing work taking heterogeneous cache coherence
from an ISCA paper to RTL to GDS
Mar 2021: Christopher Torng and Peitian Pan
prepared
an "unofficial"
artifact for HPCA'21 that includes all of the source code and
scripts for reproducing part of the results in our paper; this was
inspired by Lin Cheng preparing
an "official"
artifact for CGO'20 to earn three artifact evaluation badges and
Moyang Wang preparing
an "unofficial"
artifact for ISCA'20; even though ISCA and HPCA do not have an
"official" artifact evaluation (yet!), still very proud of our
group's effort to facilitate open and reproducible research
Feb 2021: Hosted Prof. Tony Nowatzki from
UCLA to give a talk titled "Towards General-Purpose Specialization"
as part of our H.C. Torng CSL Seminar Series
Dec 2020: Shady Agwa is finishing his
post-doc in the Batten Research Group and heading to be a Senior
Research Fellow at the University of Southampton, UK –
Congratulations!
Nov 2020: Shunning Jiang presented our
work-in-progress on implementing a universal butterfly transform
accelerator generator in PyMTL3 and Moyang Wang presented our
work-on-progress on implementing software-centric cache coherence
in scalable manycore architectures at the ADA SRC JUMP center
annual symposium
Oct 2020: Invited to present our work on
improving the performance and efficiency of deep learning recommendation
systems using PyTorch and RISC-V manycore accelerators at the
Facebook AI Systems Faculty Summit
Jun 2020: Juan Albrecht, Leandro Dorta
Duque, and Raymond Yang completed their MEng design projects and
graduated. Jaun is heading to Apple, Leo is heading to Intel, and
Juan is heading to Marvell – Congratulations!
May 2020: Shunning Jiang and Tuan Ta
prepared
a demonstration
video announcing our official PyMTL3 release as part of the ADA
SRC JUMP center annual symposium
May 2020: Most recent issue of ECE
Connections magazine includes an article about our work as part
of a large team exploring new materials, devices, circuits, and
architectures for processing-in-memory and an article about the
Computer Systems Laboratory's efforts to build a collaborative
research community
Apr 2020: BRG is
now 100% virtual but is still
making great progress on all of our research projects including a
DARPA POSH CIFER 14nm tapeout, BRGTC3 TSMC 180nm tapeout, DARPA SDH
HammerBlade Pytorch port, PyMTL3 release, and accelerators using
in-situ processing-in-SRAM
Feb 2020: Attended the Free and Open source
Software Developers' European Meeting (FOSDEM) in Brussels, Belgium
to discuss our recent work on open-source hardware
Feb 2020: Facebook proposal to explore
hardware/software co-design for deep learning recommendation systems
(with our collaborator Prof. Michael Taylor at the University of
Washington) as part of the Systems for Machine Learning program is
funded
Feb 2020: Hosted Prof. Tushar Krishna from
Georgia Tech to give a talk titled "Enabling Continuous Learning
through Synaptic Plasticity in Hardware" as part of our H.C.
Torng CSL Seminar Series
Jan 2020: Attended the DARPA IDEA/POSH
integration exercise in Salt Lake City, UT to collaboratively work
on our Python-based on-chip network generator and RTL testing
framework
Jan 2020: JUMP ADA Center seed proposals to
explore using PyMTL to implement homomorphic encryption accelerators
and integrating Spandex into the HammerBlade SoC are funded
2019
Dec 2019: Cheng Tan is finishing his
post-doc in the Batten Research Group and heading to be a
Postdoctoral Associate at the Pacific Northwest National Laboratory
– Congratulations!
Dec 2019: Co-organized a coding sprint with
Princeton University for our DARPA POSH project including
collaborative hacking on our upcoming GlobalFoundries 12nm tapeout
and a joint ski trip
Nov 2019:
Paper evaluating the
Celerity manycore (in collaboration with our colleagues at the
University of Washington, UC San Diego, University of Michigan, and
Cornell) accepted for publication in IEEE Solid-State Circuits
Letters
Oct 2019: Xiaoyu Yan received
undergraduate research funding from
the Cornell
Engineering Learning Initiatives to implement and evaluate
techniques to integrate coarse-grain configurable arrays into
manycore architectures
Sep 2019: Proposal to Xilinx for an
unrestricted industry gift to support our research is funded as
part of the Xilinx University Program
Sep 2019: Presented our work on
architectural specialization for dynamic parallel algorithms and work
stealing at
the ARM Research
Summit in Austin, TX
Jul 2019: Attended the DARPA Electronics
Research Initiative (ERI) summit in Detroit, MI to discuss on-going
work within the DARPA SDH and POSH programs
Jul 2019: Presented our work on new
processing-in-memory architectures that leverage novel
spin-orbit-torque FET devices at the DEEP3M SRC nCORE review in
Minneapolis, MN
Jun 2019: Visited Raytheon in Tucson, AZ
(along with several other PIs from the ADA SRC JUMP center) to
discuss our recent work on architectural specialization for dynamic
parallel algorithms and work stealing
Jun 2019: Research group attended the 46th
ACM/IEEE Int'l Symp. on Computer Architecture (ISCA'19) in Phoenix,
AZ
Jun 2019: The tutorial on
the new version of
PyMTL
at ISCA'19 was a great success with over 40 participants,
multiple presentations, and engaging hands-on activities
May 2019: Cameron Haire received
undergraduate summer research funding through the ECE Early Career
Research Scholars Program to develop new frameworks for testing and
evaluating computer architecture test chips – Congratulations!
May 2019: Jacob Glueck, Aaron Wisner,
Hongyi Deng, and Yixiao Zhang completed their MEng design projects
and graduated. Jacob is heading to Two Sigma, Aaron is heading to
Google, Hongyi is heading to Huawei, and Yixiao is
heading to oneZero Financial Systems – Congratulations!
May 2019: Presented our work on
architectural specialization for dynamic parallel algorithms and work
stealing and served on a panel discussing emerging technologies at
the ADA SRC JUMP center annual symposium in Ann Arbor, MI
Apr 2019: Shunning Jiang and Khalid
Al-Hawaj prepared
a demonstration video of
how PyMTL can be used not just to design chips but also to verify
these chips when they come back from the foundry
Mar 2019: Research
group's bowling night at
the Helen Newman Bowling Center
Jan 2019: Attended the DARPA IDEA/POSH
integration exercise in San Diego, CA to collaboratively work on our
Python-based on-chip network generator and RTL testing framework
Jan 2019: Cheng Tan (National University of
Singapore) and Shady Agwa (American University in Cairo) joined the
Batten Research Group as a Postdoctoral Associates – Welcome!
Oct 2018: Co-organized a hands-on activity
with Philip Bedoukian for 20 freshmen to introduce them to computer
engineering
by building
an Internet-of-things motion-detector plus alarm system
(video) as
part of the educational outreach initiatives funded through a
National Science Foundation (NSF) research grant
Oct 2018: Attended the ADA SRC JUMP center
meeting in Ann Arbor, MI
Oct 2018: Peitian Pan joined the Batten
Research Group – Welcome!
Oct 2018: Co-organized a coding sprint with
Princeton University for our DARPA POSH project including
a PyMTL
tutorial and collaborative hacking on our on-chip network
generator
Sep 2018: Raghav Kumar received
undergraduate research funding from
the Cornell
Engineering Learning Initiatives to implement and evaluate
parallel applications on task-centric architectures
Sep 2018: Presented vision for continuous
reconfiguration of polymorphic hardware (with our collaborator Prof.
Adrian Sampson) as part of the Computer Science Brown Bag Lunch
Seminar Series
Aug 2018: Yanghui Ou joined the Batten
Research Group – Welcome!
Aug 2018: Research group kicked off the
semester with a beautiful summer
hike around Beebe Lake and through the F.R. Newman Arboretum
ending at the Cornell Dairy Bar on Cornell's campus
Jul 2018: Software and hardware
infrastructure originally developed for
CURIE Academy 2014
adapted by Zhiru Zhang
for CATALYST
Academy 2018 as part of the educational outreach initiatives
funded through various National Science Foundation (NSF) grants
Jul 2018: Defense Advanced Research
Projects Agency (DARPA) proposal to develop HammerBlade, a platform
for continuous synthesis of polymorphic hardware and software (with
our collaborators Prof. Zhiru Zhang and Adrian Sampson at Cornell
University and Prof. Michael Taylor, Luis Ceze, and Mark Oskin at the
University of Washington) is funded as part of the DARPA
Software-Defined Hardware (SDH) program within the
new Electronics
Resurgence Initiative (ERI)
Jul 2018: Semiconductor Research
Corporation (SRC) proposal to explore architectures for accelerating
streaming graph processing at the edge (with our collaborator Prof.
Brandon Lucia at Carnegie Mellon University) is funded within
the Applications Driving
Architectures (ADA) center which is part of
the SRC Joint University
Microelectronics Program (JUMP)
Jun 2018: Invited (along with Berkin Ilbeyi)
to present our work on software/hardware co-design for dynamic
programming languages at King's College London and the University of
Cambridge, UK
Jun 2018: Defense Advanced Research
Projects Agency (DARPA) proposal to develop open-source IP for
cache-coherent interconnect and FPGA fabrics (with our collaborator
Prof. David Wentzlaff at Princeton University) is funded as part of
the DARPA Posh Open-Source Hardware (POSH) program within the new
Electronics
Resurgence Initiative (ERI)
May 2018: Taped out BRGTC2, our second
computer architecture test chip: a 1x1.25mm 6.7M-transistor chip in
TSMC 28nm designed and implemented using our new PyMTL hardware
modeling framework. The chip includes four RISC-V RV32IMAF cores
which share a 32KB instruction cache, 32KB data cache, and
single-precision floating point unit along with microarchitectural
mechanisms to mitigate the performance impact of resource sharing.
The chip also includes a fully synthesizable high-performance PLL
originally designed for the DARPA CRAFT project by Ian Galton and
Julian Puscar from UC San Diego. Project was led by Christopher Torng
with contributions from Shunning Jiang (core RTL design,
verification), Khalid Al-Hawaj (cache RTL design, verification), Ivan
Bukreyev (PLL porting), Berkin Ilbeyi (Bloom filter and FPU design),
Tuan Ta (CL simulation, arbiter RTL design), and Lin Cheng
(microbenchmark development).
May 2018: Featured on
the Cornell
Research site for NSF Energy-Efficient Computing: from Devices to
Architectures (E2CDA) project
May 2018: Paper on
the Celerity
system-on-chip architecture and design methodology (in
collaboration with our colleagues at the University of Washington, UC
San Diego, University of Michigan, and Cornell) published in
IEEE Micro.
Celerity was one of six systems selected out of HOTCHIPS'17 for
inclusion in this issue, and it was the only academic chip!
Apr 2018: Christopher Torng presented our
work
on enabling
rapid chip development, using our recent Celerity and BRGTC1
tapeouts as case studies, at the Computer Architecture Lab at
Carnegie Mellon University
Nov 2017: Tuan Ta joined the Batten
Research Group – Welcome!
Oct 2017: Research group alumni are
contributing to Google's recent push into building full-custom
hardware. Derek Lockhart, PhD'15, was a part of the team that
developed
Google's Cloud
Tensor Processing Unit for accelerating machine learning in the
data center. Ji Kim, PhD'16, was a part of the team that developed
Google's Pixel
Visual Core System-on-Chip for accelerating image processing in
the Pixel 2 smartphone.
Oct 2017:Research group
attended the 50th ACM/IEEE Int'l Symp. on Microarchitecture
(MICRO'17) in Cambridge, MA
Oct 2017: Source code for the
general-purpose, massively parallel, and specialization tiers in the
Celerity system-on-chip is now available online
at http://opencelerity.org
Sep 2017: Christopher Torng, Ritchie Zhao,
and Khalid Al-Hawaj presented our work on the Celerity system-on-chip
to the the Cornell
Electron Devices Society (EDS)
May 2017: Presentation on our Celerity
system-on-chip (in collaboration with UCSD and University of
Michigan) accepted to the 29th
ACM/IEEE Symp. on High-Performance Chips (HOTCHIPS'17)
May 2017: Ian Thompson, Mohammad Dohadwala,
James Talmage, and Baturay Turkmen successfully completed their MEng
design projects and graduated. Ian is heading to Green Hills
Software, Mohammad is heading to Hyperloop, James is heading to
Cavium, and Turkmen is heading to Intel – Congratulations!
May 2017: Taped out the Celerity
system-on-chip: a 5x5mm 385M-transistor chip in TSMC 16nm designed
and implemented by a large team of over 20 students and faculty from
UC San Diego, University of Michigan, and Cornell as part of
the DARPA
Circuit Realization At Faster Timescales (CRAFT) program. The
chip includes a fully synthesizable PLL, digital LDO, five modified
Chisel-generated RISC-V Rocket cores, a 496-core RISC-V tiled
manycore processor, tightly integrated Rocket-to-manycore
communication channels, complex HLS-generated BNN (binarized neural
network) accelerator, manycore-to-BNN high-speed links, sleep-mode
10-core manycore, top-level bus interconnect, high-speed
source-synchronous off-chip I/O, and a custom flip-chip package.
Cornell led the Rocket+BNN accelerator logical/physical design and
also made key contributions to the top-level logical/physical
integration and design/verification methodology.
Mar 2017: Research group moved to the new
home of the Computer Systems
Laboratory
in 471 Rhodes
Hall. The space was designed
by LEVENBETTS, a leading
architecture firm from NYC, to facilitate a sense of community,
encourage collaboration, support healthy living, and balance the
multi-dimensional aspect of academia. The space includes new Ph.D.
offices, lounge space, breakout rooms, and a state-of-the-art
hardware prototyping research lab.
Jun 2016: Defense Advanced Research
Projects Agency (DARPA) proposal to develop a synthesis methodology
for accelerator-centric SOCs and toolflows (with our collaborator
Prof. Zhiru Zhang and many others from UCSD, UCLA, and Michigan) is
funded as part of the
DARPA
Circuit Realization At Faster Timescales (CRAFT) program
Jun 2016: Berkin Ilbeyi attends
the Virtual Machines
Summer School (VMSS) at the Cumberland Lodge, UK to learn more
about JIT compilation for dynamic programming languages
May 2016: Wei Geng, Jason Setter, Taylor
Pritchard, Nagaraj Murali, and Bharath Sudheendra successfully
completed their MEng design projects and graduated. Wei and Taylor
are heading to IBM, Jason is heading to Oracle, Nagaraj is heading to
NVIDIA, and Bharath is heading to Intel – Congratulations!
Apr 2016: Taped out BRGTC1, our
first computer
architecture test chip: a 2x2mm 1.3M-transistor chip in IBM 130nm
designed and implemented using our new PyMTL hardware modeling
framework. The chip includes a simple pipelined 32-bit RISC
processor, custom LVDS clock receiver, 16KB of on-chip SRAM, and
application-specific accelerators generated using commercial C-to-RTL
high-level synthesis tools. Project was led by Christopher Torng and
Moyang Wang with contributions from Bharath Sudheendra & Nagaraj
Murali (physical design), Suren Jayasuriya & Robin Ying
(full-custom design), Shreesha Srinath (accelerator design), and
Taylor Pritchard (FPGA emulation).
Dec 2015: Khalid Al-Hawaj joined the Batten
Research Group – Welcome!
Nov 2015: Featured on
new Cornell
Research site for AFOSR award, and
on ECE
site for Cornell Engineering Research Excellence Award
Nov 2015: Received a Cornell Engineering
Research Excellence Award (one of seven awardees selected from
all engineering faculty based on recent research contributions)
Oct 2015: Shunning Jiang joined the Batten
Research Group – Welcome!
May 2015: Participated on a panel sponsored
by
the Cornell
Engineering Teaching Excellence Institute where various faculty
discussed how to prepare compelling NSF CAREER educational outreach
plans
May 2015: Alvin Wijaya, Scott McKenzie,
Kevin Lin, Andrew Chien, Asha Ganesan, and Kai Wang successfully
completed their MEng design projects and graduated. Alvin is heading
to NVIDIA, Scott is heading to Cavium, Kevin and Andrew are heading
to Intel, Asha is heading to Analog Devices, and Kai is heading to
Arista Networks – Congratulations!
Oct 2014: Moyang Wang joined the Batten
Research Group – Welcome!
Oct 2014: Research group has four papers
accepted to MICRO 2014 which represents almost 8% of the total number
of papers accepted this year to one of the premier conferences in
computer architecture
Sep
2014:CURIE
Academy 2014 website updated with photos, videos, lab materials,
and project descriptions; take a look at the
new CURIE Academy 2014
video for an overview of the week-long design experience
Jul 2014: Directed the week-long design
experience for CURIE Academy 2014
entitled "Exploring an
Internet of Things" as part of the educational outreach
initiatives funded through National Science Foundation (NSF) CAREER
grant
Jun 2014: Research group attended the 41st
ACM/IEEE Int'l Symp. on Computer Architecture (ISCA'14) in
Minneapolis, MN
May 2014: Visited the Air Force Research
Laboratory (AFRL) at Wright-Patterson Air Force Base in Dayton, OH to
learn more about various AFRL research programs
May 2014: Ackerley Tng successfully
completed his MEng design project and graduated. Ackerley is heading
to the Centre for Strategic Infocomm Technologies in Singapore
– Congratulations!
Dec 2013: Aadeetya Shreedhar, Alexander
Wang, and Edgar Munoz successfully completed their MEng design
projects and graduated. Aadeetya and Edgar are heading to Cavium and
Alexander is heading to Intel – Congratulations!
Jul 2013: Developed and led the ECE module
within
the ENGRG
1060 Explorations in Engineering summer course targeted towards
high school students; module included
a guest lecture on
Electrical and Computer Engineering and a lab session using
Arduino-based mini-robots
Jul 2013: Visited the National Science
Foundation (NSF) and Defense Advanced Research Projects Agency
(DARPA) in Arlington, VA to share recent research results
May 2013: Sampurn Pannu, John Kerr,
Christopher Fairfax, and Sean Clark successfully completed their MEng
design projects and graduated – Congratulations!
Apr 2013: Jonya Chen received undergraduate
summer research funding through the ECE Early Career Research
Scholars Program to study hardware accelerators for sorting
algorithms
Mar 2013:
The Computer Systems Lab
has five papers accepted to ISCA 2013 which represents almost 10% of
the total number of papers accepted this year to the premier
conference in computer architecture
Dec 2012: Christopher Torng selected as
a Qualcomm
Innovation Fellowship finalist along with fellow graduate student
Wacek Godycki; they will present their proposal on reconfigurable
power distribution networks this spring as part of the final
selection process – Congratulations!
Oct 2012: Christopher Torng and Berkin
Ilbeyi joined the Batten Research Group – Welcome!
Jul 2012: Developed and led the ECE module
within
the ENGRG
1060 Explorations in Engineering summer course targeted towards
high school students; module included
a guest lecture on
Electrical and Computer Engineering and a lab session using
Arduino-based mini-robots
May 2012: ECE 5950 (now ECE 5745) students
presented their
six-week
projects on complex digital ASIC design
May 2012: Gave guest lecture in CS 3410
on I/O Devices
May 2012: Gave guest lecture in ECE 3400
Electrical and Computer Engineering Practice and Design on Design
Principles and Methodologies in Computer Architecture
Apr 2012: Sean Clark and Matheus Ogleari
presented a poster on complexity-effective on-chip networks at the
Cornell ELI Undergraduate Research Poster Session
Apr 2012: Ji Kim wins the Cornell ECE
Outstanding Ph.D. Teaching award for contributions as a teaching
assistant in ECE 4750 Computer Architecture
Dec 2011: Synopsys generously provided
access to their ASIC CAD toolsuite for use in our teaching and
research as part of
the Synopsys
University Program
Sep 2011: Shreesha Srinath joined the
Batten Research Group – Welcome!
Sep 2011: Sean Clark and Matheus Ogleari
receive undergraduate research funding from Semiconductor Research
Corporation through
the Cornell
Engineering Learning Initiatives to study complexity-effective
on-chip networks
Aug 2011: Book chapter on designing
chip-level nanophotonic interconnection networks (written with our
collaborators at UC Berkeley and MIT) will be included in the
forthcoming book "Integrated Optical Interconnect Architectures and
Applications in Embedded Systems" to be published by Springer
Jun 2011: Invited to attend the Intel
Academic Leadership Summit in Santa Clara, CA
May 2011: Abhishek Aggarwal and Tejas Sapre
successfully completed their MEng design projects, graduated, and are
both heading to Intel. Yiran Yan also successfully completed his MEng
design project and is graduating this Fall – Congratulations!
Apr 2011: Big Red Chip student design team
presented their progress on a multicore processor FPGA prototype to
visiting AMD engineers
Apr 2011: Gave talk on the convergence
between general-purpose processors and data-parallel accelerators at
the Cornell Highly Integrated Physical Systems (CHIPS) annual meeting
Sep 2010: Proposal to AMD for an
unrestricted industry gift to support the Big Red Chip student
design team (co-advised with Prof. Rajit Manohar) is funded
Jul 2010: Proposal to Intel for an
unrestricted industry gift to support our research is funded
through the Intel External Programs Office
Jul 2010: Invited to give seminar on
designing nanophotonic interconnection networks to
the Cornell Electron
Devices Society (EDS)
May 2010: Joe Kerekes submitted his MEng
design project on express on-chip networks, graduated, and is heading
to Intel – Congratulations!
May 2010: ECE 5970 students presented their
four-week
design projects on chip-level interconnection networks
Apr 2010: Derek Lockhart joined the Batten
Research Group – Welcome!
