An introductory course in computer engineering that teaches the fundamental concepts of digital logic design and computer organization. Lecture topics include binary numbers, Boolean algebra, logic gates and combinational logic, sequential logic, state machines, memories, instruction set architecture, processor organization, caches and virtual memory, input/output, and case studies. Design methodology using both discrete components and hardware description languages is covered in the weekly laboratory portion of the course.
| Date |
Lecture |
Reading |
Lab |
HW/Exam |
| Tue 1/21 |
1: Course Overview [slides] [syllabus] |
1.1-1.4.2, 1.5-1.6.2 |
|
|
| Thu 1/23 |
2: Boolean Algebra [slides] |
2.1-2.3 |
|
HW 1 out |
| Tue 1/28 |
3: Combinational Logic Minimization [slides] |
2.4-2.7 |
|
|
| Wed 1/29 |
|
|
Lab 1 out |
|
| Thu 1/30 |
4: Combinational Building Blocks [slides] |
2.8 |
|
HW 2 out |
| Fri 1/31 |
|
|
|
Due: HW 1 |
| Tue 2/4 |
5: CMOS Logic [slides] |
1.7 |
|
|
| Thu 2/6 |
6: Sequential Logic: Clocks, Latches, FFs [slides] |
3.1-3.2 |
|
HW 3 out |
| Fri 2/7 |
|
|
|
Due: HW 2 |
| Tue 2/11 |
7: More Sequential Logic, Verilog [slides] |
4.1-4.5 (skip VHDL), 5.4 |
Lab 2 out |
|
| Wed 2/12 |
|
|
Due: Lab 1 |
|
| Thu 2/13 |
8: Finite State Machines (FSMs) 1 [slides] |
3.4 |
|
|
| Fri 2/14 |
|
|
|
Due: HW 3 |
| Sat 2/15 – Tue 2/18 |
— February Break — |
| Thu 2/20 |
9: FSMs 2, FSMs in Verilog [slides] |
4.6, 4.9 |
|
|
| Fri 2/21 |
|
|
Due: Prelab 2a |
|
| Tue 2/25 |
Verilog/Quartus Tutorial [slides] |
|
|
|
| Thu 2/27 |
In-class Prelim 1 @ 1:25 pm |
|
|
|
| Tue 3/4 |
10: FSMs 3, Timing, Clocking [slides] |
2.9, 3.4.4 |
|
HW 4 out |
| Wed 3/5 |
|
|
Due: Lab 2a |
|
| Thu 3/6 |
11: Timing Analysis [slides] [supplementary notes] |
3.5 |
|
|
| Mon 3/10 |
|
Lab 3 out |
|
| Tue 3/11 |
12: Timing Analysis 2; Binary Arithmetic 1 [slides] |
1.4 |
|
|
| Wed 3/12 |
|
|
Due: Lab 2b |
|
| Thu 3/13 |
13: Binary Arithmetic 2, ALU [slides] |
5.1-5.2.4 |
|
HW 5 out |
| Fri 3/14 |
|
|
|
Due: HW 4 |
| Mon 3/17 |
|
|
Due: Prelab 3a |
|
| Tue 3/18 |
14: ROM, SRAM, and DRAM [slides] |
5.5 |
|
|
| Wed 3/19 |
|
|
Due: Lab 3a |
|
| Thu 3/20 |
15: Single Cycle Microprocessor 1 [slides] |
7.1-7.3.4 |
|
HW 6 out |
| Fri 3/21 |
|
|
|
Due: HW 5 |
| Mon 3/24 |
|
|
Due: Prelab 3b |
|
| Tue 3/25 |
16: Single Cycle Microprocessor 2 [slides] |
7.3 |
|
|
| Wed 3/26 |
|
|
Due: Lab 3b |
|
| Thu 3/27 |
17: Pipelined Microprocessor 1 [slides] |
7.5.1-7.5.2 |
|
|
| Fri 3/28 |
|
|
|
Due: HW 6 |
| Sat 3/29 – Sun 4/6 |
— Spring Break — |
| Mon 4/7 |
|
|
Lab 4 out |
|
| Tue 4/8 |
18: Pipelined Microprocessor 2 [slides] |
7.5.3-7.5.4 |
|
|
| Thu 4/10 |
19: Pipelined Microprocessor 3 [slides] |
|
|
Prelim 2 @ 7:30 pm, GSH G76 |
| Mon 4/14 |
|
|
Due: Prelab 4a |
|
| Tue 4/15 |
20: Caches and Main Memory 1 [slides] |
8-8.3 |
|
|
| Wed 4/16 |
|
|
Due: Lab 4a |
|
| Thu 4/17 |
21: Caches 2 [slides] |
8.3 |
HW 7 out |
|
| Fri 4/18 |
|
|
Due: Lab 3 report |
|
| Tue 4/22 |
22: Caches 3 [slides] |
8.3 |
|
|
| Wed 4/23 |
|
|
Due: Lab 4b |
|
| Thu 4/24 |
23: Performance Tradeoffs [slides] |
7.5.4, 8.2 |
|
HW 8 out |
| Fri 4/25 |
|
|
Lab 5 out |
Due: HW 7 |
| Mon 4/28 |
|
|
Due: Lab 4c |
|
| Tue 4/29 |
24: Virtual Memory [slides] |
8.4 |
|
|
| Wed 4/30 |
|
|
Due: Lab 4 report |
|
| Thu 5/1 |
25: Exceptions, Input/Output [slides] |
6.6.2, 9.2, 9.3.8 |
|
|
| Fri 5/2 |
|
|
|
Due: HW 8 |
| Mon 5/5 |
|
|
Due: Lab 5 |
|
| Tue 5/6 |
26: Advanced Topics [slides] |
|
|
|
Sat 5/10 |
|
Final exam @ 9:00am, PHL 101 |
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