office: 323 Rhodes Hall, Ithaca, NY 14853
phone: (607) 255-2672
email: cbatten cornell edu
I am a Professor of Electrical and Computer Engineering and a graduate field member of Computer Science at Cornell University. I am currently on sabbatical as a Visiting Scholar at the University of California, Berkeley working in the SLICE Lab. In spring of 2024, I will be a Visiting Professor at NVIDIA working in the ASIC & VLSI Research Group.
My research group at Cornell is part of the Computer Systems Laboratory, and we largely work at the intersection of computer architecture, electronic design automation, and digital VLSI including projects on parallel programming frameworks, programmable accelerator design, interconnection networks, productive VLSI chip design methodologies, and architectures for future emerging technologies. Building prototype systems is an integral part of my research, as this is one of the best ways to validate assumptions, gain intuition about physical design issues, and provide platforms for future software research.
My research has been recognized with several awards including the ACM/IEEE MICRO Hall of Fame, a Cornell Engineering Research Excellence Award, an AFOSR Young Investigator Program award, an Intel Early Career Faculty Honor Program award, an NSF CAREER award, a DARPA Young Faculty Award, and an IEEE Micro Top Picks selection. My teaching has been recognized with the Ruth and Joel Spira Award for Excellence in Teaching, a Kenneth A. Goldman '71 Teaching Award, two Michael Tien '72 Excellence in Teaching Awards, and a James M. and Marsha D. McCormick Award for Outstanding Advising of First-Year Engineering Students.
In 2018, I was a Visiting Scholar at the Computer Laboratory at the University of Cambridge and a Visiting Fellow at Clare Hall in Cambridge, UK. Prior to joining Cornell University, I received my Ph.D. in Electrical Engineering and Computer Science from the Massachusetts Institute of Technology. I received an M.Phil. in Engineering as a Churchill Scholar at the University of Cambridge in 2000, and received a B.S. in Electrical Engineering as a Jefferson Scholar at the University of Virginia in 1999.
- Nov 2023: Attended the RISC-V Summit in Santa Clara, CA and the NSF CHIPS Education and Workforce Development Convening in Washington, DC
- Oct 2023: Paper on supporting a virtual vector instruction set on a commercial compute-in-SRAM accelerator is accepted to the 2nd Workshop on Democratizing Domain-Specific Accelerators (WDDSA'23) to be held in conjunction with MICRO-56
- Oct 2023: National Science Foundation (NSF) proposal to advance computer systems research capability, reproducibility, and sustainability with the gem5 simulator ecosystem (led by Jason Lowe-Power at UC Davis and with our collaborators at the University of Washington, the University of Wisconsin, the University of Kansas, and Georgia Tech) is funded as part of the NSF Cyberinfrastructure for Sustained Scientific Innovation (CSSI) program
- Sep 2023: Presented our work on formal verification of the stall invariant property for latency-insensitive RTL modules at the 21st ACM/IEEE Int'l Symp. on Formal Methods and Models for System Design (MEMOCODE'23) in Hamburg, Germany
- Sep 2023: Presented our work on checking generator properties in dynamic HDLs using symbolic elaboration at the 21st ACM/IEEE Int'l Symp. on Formal Methods and Models for System Design (MEMOCODE'23) in Hamburg, Germany
- Sep 2023: Invited to present our vision for a new era of open-source hardware, using our work on PyMTL3 as a case study, at the Universtat Politècnica de Catalunya (UPC) and the Barcelona Supercomputing Center (BSC) in Barcelona, Spain
- Sep 2023: Visited Michael Taylor's research group at the University of Washington to see the rack-scale RISC-V manycore prototype being developed as part of our NSF Panorama project
- Sep 2023: Received the Kenneth A. Goldman '71 Teaching Award (one of the highest award for teaching in the College of Engineering at Cornell University)
- Sep 2023: Attended the DARPA Electronics Research Initiative (ERI) summit in Seattle, WA and the Symp. on High-Performance Chips (HOTCHIPS) at Stanford
- Aug 2023: Started sabbatical as a visiting scholar at the SLICE Lab at the University of California, Berkeley
- Aug 2023: Paper on formal verification of the stall invariant property for latency-insensitive RTL modules accepted to the 21st ACM/IEEE Int'l Symp. on Formal Methods and Models for System Design (MEMOCODE'23)
- Aug 2023: Paper on checking generator properties in dynamic HDLs using symbolic elaboration accepted to the 21st ACM/IEEE Int'l Symp. on Formal Methods and Models for System Design (MEMOCODE'23)
- Aug 2023: Paper evaluating the CIFER system-on-chip (in collaboration with our colleagues at Princeton University) accepted for publication in IEEE Solid-State Circuits Letters
- Aug 2023: Austin Rovinski is finishing his post-doc in the Batten Research Group and heading to be an Assistant Professor at New York University – Congratulations!
- Jul 2023: Tuan Ta successfully defended his doctoral thesis titled "Evolutionary Hardware Specialization for Modern Vector and Matrix Architectures". Tuan is heading to Tenstorrent – Congratulations!
- Jul 2023: Paper on new instruction set extensions for fast, scalable, and efficient genome sequence alignment (in collaboration with our colleagues at the Universitat Politecnica de Catalunya and Barcelona Supercomputing Center) accepted to the 56th ACM/IEEE Int'l Symp. on Microarchitecture (MICRO'23)
- Jul 2023: Photos from the CSL retreat posted on the retreat webpage
- Jul 2023: Served as the selection committee co-chair (with Jae Lee at the Seoul National University) for the IEEE Micro Top Picks 2023 special issue which is now published; the issue includes some of the very best recent research in the field of computer architecture in terms of novelty and potential for long-term impact.
- Jul 2023: The ECE 5745 test chips came back; the chip was fabricated on SkyWater 130nm through the efabless ChipIgnite program. The chip included four projects with 15 students participating: a CRC32 checksum unit, a latency insensitive synthesizable memory, a 2x2 systolic array multiplier, and a greatest common divisor unit.
- Jun 2023: Courtney Golden presented our work on accelerating seed location filtering in DNA read mapping using a commercial compute-in-SRAM architecture at the 5th Workshop on Accelerator Architecture in Computational Biology and Bioinformatics (AACBB'23) in Orlando, FL
- Jun 2023: Research group attended the 50th ACM/IEEE Int'l Symp. on Computer Architecture (ISCA'23) in Orlando, FL including a chance to catch up with BRG alumni Christopher Torng and Derek Lockhart
- Jun 2023: The student-led Cornell Custom Silicon Systems (C2S2) project team successfully taped out two chips on SkyWater 130nm through the efabless ChipIgnite program; an analog test chip includes two variants of a full-custom op-amp and a separate digital test chip includes a 32-point fast Fourier transform accelerator with corresponding SPI interfaces to read input data from a microphone and output the corresponding frequency-domain signal.
- May 2023: Attended MemPanG23, a hands-on course on computational pangenomics held at the University of Tennessee Health Science Center in Memphis, TN
- May 2023: Anya Prabowo, Bryce Roth, Dhruv Sharma, and Megha Shyam completed their MEng design projects and graduated. Anya is heading to NVIDIA; Bryce is heading to Miter, and Megha is heading to Apple – Congratulations!
- May 2023: Co-organized the Computer Systems Laboratory Retreat at the Moakley House with over 60 attendees, two distinguished keynote speakers, an alumni panel, student research talks, and a poster session
- May 2023: Gave guest lecture in ENGRI 1210 The Computing Technology Inside Your Smartphone on Recent Trends in Computer Engineering
- Apr 2023: Paper on accelerating seed location filtering in DNA read mapping using a commercial compute-in-SRAM architecture (in collaboration with Dan Ilan at GSI Technologies) is accepted to the 5th Workshop on Accelerator Architecture in Computational Biology and Bioinformatics (AACBB'23) to be held in conjunction with ISCA-50
- Mar 2023: Invited to present work on PyMTL3 at NVIDIA research
- Mar 2023: Courtney Golden was selected as a Merrill Presidential Scholar, which is awarded to the most outstanding graduating seniors at Cornell, and also earned a National Science Foundation (NSF) Graduate Research Fellowship – Congratulations!
- Mar 2023: Peitian Pan presented our work on gradually typed hardware description languages at the Workshop on Languages, Tools, and Techniques for Accelerator Design (LATTE'23) in Vancouver, CA
- Mar 2023: Co-organized field trip for the Cornell Custom Silicon Systems (C2S2) team to visit the SUNY Poly Nanoscale Fabrication Facility in Albany, NY
- Feb 2023: Paper making the case for gradually typed hardware description languages is accepted to the Workshop on Languages, Tools, and Techniques for Accelerator Design (LATTE'23) to be held in conjunction with ASPLOS-28
- Feb 2023: Khalid Al-Hawaj presented our work on ephemeral vector engines at the 29th IEEE Int'l Symp. on High-Performance Computer Architecture (HPCA'23) in Montreal, CA
- Feb 2023: Promoted to the rank of Full Professor by the Cornell University Board of Trustees
- Jan 2023: Paper on supporting dynamic task parallelism on manycore architectures with software-managed scratchpad memories (in collaboration with our colleagues at the University of Washington) accepted for publication in the ACM Int'l Conf. on Architectural Support for Programming Languages and Operating System (ASPLOS'23)
- Jan 2023: Paper evaluating the CIFER system-on-chip (in collaboration with our colleagues at Princeton University) accepted for publication in the IEEE Custom Integrated Circuits Conf. (CICC'23); CIFER is a 4x4mm 456M-transistor chip in GlobalFoundries 12nm which includes four RISC-V RV64GC Ariane cores (implemented using SystemVerilog), 18 RISC-V RV32IM tiny cores (implemented using PyMTL3), and an embedded FPGA (implemented using PRGA) interconnected through a heterogeneous cache coherent memory system.
- Jan 2023: Course website for ECE 5745 Complex Digital ASIC Design now online
- Dec 2022: Jack Brzozowski, Kyle Infantino, Dilan Lakhani, Angela Zou, and Lauren Shen completed their MEng design projects and graduated. Jack is heading to AMD; Kyle, Dilan, and Lauren are heading to Apple; and Angela is heading to Qualcomm – Congratulations!
- Dec 2022: Research group celebrated with an end-of-semester dinner
- Dec 2022: Co-advising the brand new Cornell Custom Silicon Systems (C2S2) project team. C2S2 is a student-led team of 25 diverse students including sophomores, juniors, and seniors organized into six subteams focusing on digital design and verification, analog design, software, system architecture, and project management. C2S2 is working hard towards their first tapeout on SkyWater 130nm this spring!
- Dec 2022: Article on Jack Brozozowski, Kyle Infantino, and Dilan Lakhani's MEng design project which involved designing, testing, fabricating, and testing a custom RISC-V microcontroller in TSMC 180nm published as an ECE spotlight news item
- All News
- ECE 2400 Computer Systems Programming
- ECE 4750 Computer Architecture
- ECE 5745 Complex Digital ASIC Design
- ECE 5970 Special Topics: Chip-Level Interconnection Networks
Educational Outreach Activities
- CSMore: Week-Long Computer Systems Unit
- Curie Academy 2021: Week-Long Design Experience
- ENGRG 1050 Engineering Seminar: Computer Engineering Hands-On Experience
- ENGRG 1060 Explorations in Engineering: Computer Engineering Unit
- Curie Academy 2014: Week-Long Design Experience
- Yanghui Ou (MS/PhD)
- Peitian Pan (MS/PhD)
- Nick Cebry (MS/PhD)
- Former Members
- National Science Foundation: CSSI'23, PPoSS'21, SHF'20/'15, E2CDA'17
- National Science Foundation: CRI'15/'11, XPS'13, EAGER'11, CAREER'12
- Defense Advanced Research Projects Agency: PIPES'21, POSH'18, SDH'18, CRAFT'16, YFA'12
- Air Force Office of Scientific Research: YIP'15
- Semiconductor Research Corporation: JUMP'18, E2CDA'17
- Intel Corporation: research funding and equipment donation
- Facebook: research funding
- NVIDIA: research funding and equipment donation
- Xilinx: research funding and CAD tool donation
- Cornell Engineering Learning Initiatives: undergraduate research funding
- Advanced Micro Devices: undergraduate research funding
- Synopsys, Cadence, Mentor: CAD tool donation
- ARM: physical IP donation
- GitHub, TravisCI, Codecov.io: hosted software donations
- Conference PC Chair: IEEE Micro TopPicks'23
- Conference PC Member: IEEE Micro TopPicks'22/'16, ISCA'22/'17/'15/'13, MICRO'20/'15
- Conference PC Member: SC'17/'16, HPCA'16, PPoPP'13, ASPLOS'11
- Conference External Reviewer: ISCA, ASPLOS, MICRO, HPCA, DAC, SIGMETRICS
- Conference Organizing Committee Member: HPCA'14
- Workshop PC Member: WDDD'16, GPGPU'16, NOPE'15, WDDD'15, GPGPU'14
- Workshop Co-Organizer: SIGARCH Visioning Workshop on Open and Agile HW Design, WARP'15, WINDS'10
- Tutorial Co-Organizer: PyMTL'19, PyMTL/Pydgin'15
- Associate Editor: IEEE Micro'20–23
- Journal Reviewer: IEEE Micro, CACM, JETCAS, TCAD, TVLSI, TACO, CAL, MICPRO, COMPUTER
- Book Reviewer: Morgan and Claypool Synthesis Lectures on Computer Architecture
- Member: IEEE Computer Society, ACM SIGARCH