2018

  • [C45] W. Hua, Z. Zhang, and G. E. Suh, Reverse Engineering Convolutional Neural Networks Through Side-channel Information Leaks, to appear in Design Automation Conference (DAC), Jun. 2018.
  • [M1] W. Hua, C. De Sa, Z. Zhang, and G. E. Suh, Channel Gating Neural Networks, arXiv e-print, arXiv:1805.12549, May 2018.
  • [C44] S. Dai, Y. Zhou, H. Zhang, E. Ustun, E. F.Y. Young, and Z. Zhang, Fast and Accurate Estimation of Quality of Results in High-Level Synthesis with Machine Learning, International Symposium on Field-Programmable Custom Computing Machines (FCCM), Apr./May 2018. (Best Paper Award, short paper category)
  • [J8] S. Davidson, S. Xie, C. Torng, K. Al-Hawai, A. Rovinski, T. Ajayi, L. Vega, C. Zhao, R. Zhao, S. Dai, A. Amarnath, B. Veluri, P. Gao, A. Rao, G. Liu, R. Gupta, Z. Zhang, R. Dreslinski, C. Batten, and M. Taylor, The Celerity Open-Source 511-Core RISC-V Tiered Accelerator Fabric: Fast Architectures and Design Methodologies for Fast Chips, IEEE Micro, Mar/Apr. 2018.
  • [C43] S. Dai, G. Liu, and Z. Zhang, A Scalable Approach to Exact Resource-Constrained Scheduling Based on a Joint SDC and SAT Formulation, International Symposium on Field-Programmable Gate Arrays (FPGA), Feb. 2018. (Best Paper Nominee)
  • [C42] Y. Zhou, U. Gupta, S. Dai, R. Zhao, N. Srivastava, H. Jin, J. Featherston, Y.-H. Lai, G. Liu, G. Velasquez, W. Wang, and Z. Zhang, Rosetta: A Realistic High-Level Synthesis Benchmark Suite for Software Programmable FPGAs, International Symposium on Field-Programmable Gate Arrays (FPGA), Feb. 2018.

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