2017

  • [J7] G. Liu, M. Tan, S. Dai, R. Zhao, and Z. Zhang, Architecture and Synthesis for Area-Efficient Pipelining of Irregular Loop Nests, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Feb. 2017.
  • [C37] G. Liu and Z. Zhang, A Parallelized Iterative Improvement Approach to Area Optimization for LUT-Based Technology Mapping, International Symposium on Field-Programmable Gate Arrays (FPGA), Feb. 2017. (Best Paper Nominee)
  • [C36] Y. Zhou, K. Al-Hawaj, and Z. Zhang, A New Approach to Automatic Memory Banking using Trace-Based Address Mining, International Symposium on Field-Programmable Gate Arrays (FPGA), Feb. 2017.
  • [C35] R. Zhao, W. Song, W. Zhang, T. Xing, J.-H. Lin, M. Srivastava, R. Gupta, and Z. Zhang, Accelerating Binarized Convolutional Neural Networks with Software-Programmable FPGAs, International Symposium on Field-Programmable Gate Arrays (FPGA), Feb. 2017.
  • [C34] C. Xu, G. Liu, R. Zhao, S. Yang, G. Luo, and Z. Zhang, A Parallel Bandit-Based Approach for Autotuning FPGA Compilation, International Symposium on Field-Programmable Gate Arrays (FPGA), Feb. 2017.
  • [C33] S. Dai, R. Zhao, G. Liu, S. Srinath, U. Gupta, C. Batten, and Z. Zhang, Dynamic Hazard Resolution for Pipelining Irregular Loops in High-Level Synthesis, International Symposium on Field-Programmable Gate Arrays (FPGA), Feb. 2017.
  • [C32] N. Srivastava, S. Dai, R. Manohar, and Z. Zhang, Accelerating Face Detection on Programmable SoC Using C-Based Synthesis, International Symposium on Field-Programmable Gate Arrays (FPGA), Feb. 2017.

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