Zhiru Zhang

2019

• [C47] Y.-H. Lai, Y. Chi, Y. Hu, J. Wang, C. H. Yu, Y. Zhou, J. Cong, and Z. Zhang, HeteroCL: A Multi-Paradigm Programming Infrastructure for Software-Defined Reconfigurable Computing, to appear in International Symposium on Field-Programmable Gate Arrays (FPGA), Feb. 2019.

2018

• [A2] R. Zhao, Y. Hu, J. Dotzel, C. De Sa, and Z. Zhang, Building Efficient Deep Neural Networks with Unitary Group Convolutions, arXiv e-print, arXiv:1811.07755, Nov. 2018.
• [C46] Z. Jiang, S. Dai, G. E. Suh, and Z. Zhang, High-Level Synthesis with Timing-Sensitive Information Flow Enforcement, International Conference On Computer Aided Design (ICCAD), Nov. 2018.
• [C45] W. Hua, Z. Zhang, and G. E. Suh, Reverse Engineering Convolutional Neural Networks Through Side-channel Information Leaks, Design Automation Conference (DAC), Jun. 2018.
• [A1] W. Hua, C. De Sa, Z. Zhang, and G. E. Suh, Channel Gating Neural Networks, arXiv e-print, arXiv:1805.12549, May 2018.
• [C44] S. Dai, Y. Zhou, H. Zhang, E. Ustun, E. F.Y. Young, and Z. Zhang, Fast and Accurate Estimation of Quality of Results in High-Level Synthesis with Machine Learning, International Symposium on Field-Programmable Custom Computing Machines (FCCM), Apr./May 2018. (Best Paper Award, short paper category)
• [J8] S. Davidson, S. Xie, C. Torng, K. Al-Hawai, A. Rovinski, T. Ajayi, L. Vega, C. Zhao, R. Zhao, S. Dai, A. Amarnath, B. Veluri, P. Gao, A. Rao, G. Liu, R. Gupta, Z. Zhang, R. Dreslinski, C. Batten, and M. Taylor, The Celerity Open-Source 511-Core RISC-V Tiered Accelerator Fabric: Fast Architectures and Design Methodologies for Fast Chips, IEEE Micro, Mar/Apr. 2018.
• [C43] S. Dai, G. Liu, and Z. Zhang, A Scalable Approach to Exact Resource-Constrained Scheduling Based on a Joint SDC and SAT Formulation, International Symposium on Field-Programmable Gate Arrays (FPGA), Feb. 2018. (Best Paper Nominee)
• [C42] Y. Zhou, U. Gupta, S. Dai, R. Zhao, N. Srivastava, H. Jin, J. Featherston, Y.-H. Lai, G. Liu, G. Velasquez, W. Wang, and Z. Zhang, Rosetta: A Realistic High-Level Synthesis Benchmark Suite for Software Programmable FPGAs, International Symposium on Field-Programmable Gate Arrays (FPGA), Feb. 2018.

2017

• [C41] G. Liu and Z. Zhang, Statistically Certified Approximate Logic Synthesis, International Conference on Computer-Aided Design (ICCAD), Nov. 2017.
• [C40] S. Dai, G. Liu, R. Zhao, and Z. Zhang, Enabling Adaptive Loop Pipelining in High-Level Synthesis, 52nd Annual Asilomar Conference on Signals, Systems, and Computers, Oct. 2017. (Invited Paper)
• [W4] T. Ajayi, K. Al-Hawaj, A. Amarnath, S. Dai, S. Davidson, P. Gao, G. Liu, A. Rao, A. Rovinski, N. Sun, C. Torng, L. Vega, B. Veluri, S. Xie, C. Zhao, R. Zhao, C. Batten, R. Dreslinski, R. Gupta, M. Taylor, and Z. Zhang, Experiences Using the RISC-V Ecosystem to Design an Accelerator-Centric SoC in TSMC 16nm, First Workshop on Computer Architecture Research with RISC-V (CARRV), Oct. 2017.
• [C39] T. Ajayi, K. Al-Hawaj, A. Amarnath, S. Dai, S. Davidson, P. Gao, G. Liu, A. Lotfi, J. Puscar, A. Rao, A. Rovinski, L. Salem, N. Sun, C. Torng, L. Vega, B. Veluri, X. Wang, S. Xie, C. Zhao, R. Zhao, C. Batten, R. Dreslinski, I. Galton, R. Gupta, P. Mercier, M. Srivastava, M. Taylor, and Z. Zhang, Celerity: An Open-Source RISC-V Tiered Accelerator Fabric, ACM/IEEE Symposium on High-Performance Chips (HOTCHIPS), Aug. 2017.
• [W3] J.H. Lin, T. Xing, R. Zhao, Z. Zhang, M. Srivastava, Z. Tu, and R. Gupta, Binarized Neural Networks with Separable Filters for Efficient Hardware Acceleration, IEEE Conference on Computer Vision and Pattern Recognition Workshops (CVPRW), Jul. 2017.
• [C38] E. Bartz, J. Chaves, Y. Gershtein, E. Halkiadakis, M. Hildreth, S. Kyriacou, K. Lannon, A. Lefeld, A. Ryd, L. Skinnari, R. Stone, C. Strohman, Z. Tao, B. Winer, P. Wittich, Z. Zhang, and M. Zientek, FPGA-based Real-time Charged Particle Trajectory Reconstruction at the Large Hadron Collider, International Symposium on Field-Programmable Custom Computing Machines (FCCM), May 2017.
• [C37] G. Liu and Z. Zhang, A Parallelized Iterative Improvement Approach to Area Optimization for LUT-Based Technology Mapping, International Symposium on Field-Programmable Gate Arrays (FPGA), Feb. 2017. (Best Paper Nominee)
• [C36] Y. Zhou, K. Al-Hawaj, and Z. Zhang, A New Approach to Automatic Memory Banking using Trace-Based Address Mining, International Symposium on Field-Programmable Gate Arrays (FPGA), Feb. 2017.
• [C35] R. Zhao, W. Song, W. Zhang, T. Xing, J.-H. Lin, M. Srivastava, R. Gupta, and Z. Zhang, Accelerating Binarized Convolutional Neural Networks with Software-Programmable FPGAs, International Symposium on Field-Programmable Gate Arrays (FPGA), Feb. 2017.
• [C34] C. Xu, G. Liu, R. Zhao, S. Yang, G. Luo, and Z. Zhang, A Parallel Bandit-Based Approach for Autotuning FPGA Compilation, International Symposium on Field-Programmable Gate Arrays (FPGA), Feb. 2017.
• [C33] S. Dai, R. Zhao, G. Liu, S. Srinath, U. Gupta, C. Batten, and Z. Zhang, Dynamic Hazard Resolution for Pipelining Irregular Loops in High-Level Synthesis, International Symposium on Field-Programmable Gate Arrays (FPGA), Feb. 2017.
• [C32] N. Srivastava, S. Dai, R. Manohar, and Z. Zhang, Accelerating Face Detection on Programmable SoC Using C-Based Synthesis, International Symposium on Field-Programmable Gate Arrays (FPGA), Feb. 2017.
• [J7] G. Liu, M. Tan, S. Dai, R. Zhao, and Z. Zhang, Architecture and Synthesis for Area-Efficient Pipelining of Irregular Loop Nests, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Feb. 2017.

2016

• [J6] D. Chen, J. Cong, S. Gurumani, W-M. Hwu, K. Rupnow, and Z. Zhang, Platform Choices and Design Demands for IoT Platforms: Cost, Power and Performance Tradeoffs, IET Cyber-Physical Systems: Theory & Applications (IET-CPS), Nov. 2016.
• [C31] R. Zhao, G. Liu, S. Srinath, C. Batten, and Z. Zhang, Improving High-Level Synthesis with Decoupled Data Structure Optimization, Design Automation Conference (DAC), Jun. 2016.
• [C30] A. Majumdar, Z. Zhang, and D. Albonesi, Characterizing the Benefits and Limitations of Smart Building Meeting Room Scheduling, International Conference on Cyber-Physical Systems (ICCPS), Apr. 2016.
• [W2] D. Chen, J. Cong, S. Gurumani, W-M. Hwu, K. Rupnow, and Z. Zhang, System Synthesis and Automated Verification: Design Demands for IoT Devices, Sensors to Cloud Architectures Workshop (SCAW), Mar. 2016.

2015

• [C29] F. Koushanfar, A. Mirhoseini, G. Qu, and Z. Zhang, DA Systemization of Knowledge: A Catalog of Prior Forward-Looking Initiatives, International Conference on Computer-Aided Design (ICCAD), Nov. 2015. (Invited Paper)
• [C28] M. Tan, G. Liu, R. Zhao, S. Dai, and Z. Zhang, ElasticFlow: A Complexity-Effective Approach for Pipelining Irregular Loop Nests, International Conference on Computer-Aided Design (ICCAD), Nov. 2015.
• [C27] G. Liu and Z. Zhang, A Reconfigurable Analog Substrate for Highly Efficient Maximum Flow Computation, Design Automation Conference (DAC), Jun. 2015.
• [C26] R. Zhao, M. Tan, S. Dai, and Z. Zhang, Area-Efficient Pipelining for FPGA-Targeted High-Level Synthesis, Design Automation Conference (DAC), Jun. 2015.
• [C25] M. Tan, S. Dai, U. Gupta, and Z. Zhang, Mapping-Aware Constrained Scheduling for LUT-Based FPGAs, International Symposium on Field-Programmable Gate Arrays (FPGA), Feb. 2015.
• [J5] Z. Zhang, D. Chen, S. Dai, and K. Campbell, High-Level Synthesis for Low-Power Design, IPSJ Transactions on System LSI Design Methodology (T-SLDM), Feb. 2015. (Invited Paper)

2014

• [C24] S. Srinath, B. Ilbeyi, M. Tan, G. Liu, Z. Zhang, and C. Batten, Architectural Specialization for Inter-Iteration Loop Dependence Patterns, International Symposium on Microarchitecture (MICRO), Dec. 2014.
• [C23] M. Tan, B. Liu, S. Dai, and Z. Zhang, Multithreaded Pipeline Synthesis for Data-Parallel Kernels, International Conference on Computer-Aided Design (ICCAD), Nov. 2014.
• [C22] G. Liu, Y. Tao, M. Tan, and Z. Zhang, CASA: Correlation-Aware Speculative Adders, International Symposium on Low Power Electronics and Design (ISLPED), Aug. 2014.
• [C21] S. Dai, M. Tan, K. Hao, and Z. Zhang, Flushing-Enabled Loop Pipelining for High-Level Synthesis, Design Automation Conference (DAC), Jun. 2014.

2013

• [C20] Z. Zhang and B. Liu, SDC-Based Modulo Scheduling for Pipeline Synthesis, International Conference on Computer-Aided Design (ICCAD), Nov. 2013.

2012

• [C19] Z. Zhang and D. Chen, Challenges and Opportunities of ESL Design Automation, International Conference on Solid-State and Integrated Circuit Technology (ICSICT), Oct. 2012. (Invited Paper)

2011

• [J4] J. Cong, B. Liu, S. Neuendorffer, J. Noguera, K. Vissers, and Z. Zhang, High-Level Synthesis for FPGAs: From Prototyping to Deployment, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 30(4):473–491, Apr. 2011. (Keynote Paper)

2010

• [J3] J. Cong, B. Liu, R. Majumdar, and Z. Zhang, Behavior-Level Observability Analysis and Operation Gating in Low-Power Behavioral Synthesis, ACM Transactions on Design Automation of Electronic Systems (TODAES), 16(1):1–29, Nov. 2010. (Best Paper Award)
• [C18] J. Zhang, Z. Zhang, S. Zhou, M. Tan, X. Liu, X. Cheng, and J. Cong, Bit-Level Optimization for High-Level Synthesis and FPGA-Based Acceleration, International Symposium on FPGAs (FPGA), Feb. 2010.

2009

• [C17] J. Cong, B. Liu, and Z. Zhang, Scheduling with Soft Constraints, International Conference on Computer-Aided Design (ICCAD), Nov 2009. (Best Paper Nominee)
• [C16] J. Cong, B. Liu, and Z. Zhang, Behavior-Level Observability Don't-Cares and Application to Low-Power Behavioral Synthesis, International Symposium on Low Power Electronics and Design (ISLPED), Aug. 2009.
• [W1] J. Zhang, Z. Zhang, S. Zhou, M. Tan, X. Liu, X. Cheng, and J. Cong, Bit-Level Transformation and Optimization for Hardware Synthesis of Algorithmic Descriptions, International Workshop on Logic & Synthesis (IWLS), Aug. 2009.
• [C15] J. Cong, K. Gururaj, B. Liu, C. Liu, Z. Zhang, S. Zhou, and Y. Zou, Evaluation of Static Analysis Techniques for Fixed-Point Precision Optimization, IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), Apr. 2009.

2008

• [B1] Z. Zhang, Y. Fan, W. Jiang, G. Han, C. Yang, and J. Cong, AutoPilot: A Platform-Based ESL Synthesis System, High-Level Synthesis: From Algorithm to Digital Circuit, ed. P. Coussy and A. Morawiec, Springer Publishers, 2008.
• [C14] W. Jiang, Z. Zhang, M. Potkonjnak, and J. Cong, Scheduling with Integer Time Budgeting for Low-Power Optimization, Asia and South Pacific Design Automation Conference (ASP-DAC), Jan. 2008.
• [C13] C.T. Hsieh, J. Cong, S.C. Chang, and Z. Zhang, Behavioral Synthesis with Activating Unused Flip-Flops for Reducing Glitch Power in FPGA, Asia and South Pacific Design Automation Conference (ASP-DAC), Jan. 2008.

2007

• [C12] D. Chen, J. Cong, Y. Fan, and Z. Zhang, High-Level Power Estimation and Low-Power Design Space Exploration for FPGAs, Asia and South Pacific Design Automation Conference (ASP-DAC), Jan. 2007.

2006

• [J2] J. Cong, G. Han, and Z. Zhang, Architecture and Compiler Optimization for Data Bandwidth Improvement in Configurable Processors, IEEE Transaction on Very Large Scale Integration Systems (TVLSI), 14(9):986–997, Sept. 2006.
• [C11] J. Cong, Y. Fan, G. Han, W. Jiang, and Z. Zhang, Platform-Based Behavior-Level and System-Level Synthesis, IEEE International SOC Conference (SOCC), Sept. 2006. (Invited Paper)
• [C10] J. Cong and Z. Zhang, An Efficient and Versatile Scheduling Algorithm Based on SDC Formulation, Design Automation Conference (DAC), Jul. 2006.
• [C9] J. Cong, Y. Fan, G. Han, W. Jiang, and Z. Zhang, Behavior and Communication Co-Optimization for Systems with Sequential Communication Media, Design Automation Conference (DAC), Jul. 2006.

2005

• [C8] J. Cong, G. Han, and Z. Zhang, Architecture and Compilation for Data Bandwidth Improvement in Configurable Embedded Processors, International Conference on Computer-Aided Design (ICCAD), Nov. 2005.
• [C7] J. Cong, Y. Fan, G. Han, A. Jagannathan, G. Reinman, and Z. Zhang, Instruction Set Extension with Shadow Registers for Configurable Processors, International Symposium on FPGAs (FPGA), Feb. 2005.
• [C6] J. Cong, Y. Fan, G. Han, Y. Lin, J. Xu, Z. Zhang, and X. Cheng, Bitwidth-Aware Scheduling and Binding in High-Level Synthesis, Asia and South Pacific Design Automation Conference (ASP-DAC), Jan. 2005.

2004

• [C5] J. Cong, Y. Fan, and Z. Zhang, Architecture-Level Synthesis for Automatic Interconnect Pipelining, Design Automation Conference (DAC), Jun. 2004.
• [J1] J. Cong, Y. Fan, G. Han, X. Yang, and Z. Zhang, Architecture and Synthesis for On-Chip Multicycle Communication, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 23(4):550–564, Apr. 2004.
• [C4] J. Cong, Y. Fan, G. Han, and Z. Zhang, Application-Specific Instruction Generation for Configurable Processor Architectures, International Symposium on Field-Programmable Gate Arrays (FPGA), Feb. 2004. (Among the Top 10 most-cited articles from FPGA symposium since 1995)

2003

• [C3] J. Cong, Y. Fan, G. Han, X. Yang, and Z. Zhang, Architectural Synthesis Integrated with Global Placement for Multi-Cycle Communication, International Conference on Computer-Aided Design (ICCAD), Nov. 2003.
• [C2] Z. Zhang, Y. Fan, M. Potkonjak, and J. Cong, Gradual Relaxation Technique with Application to Behavioral Synthesis, International Conference on Computer-Aided Design (ICCAD), Nov. 2003.
• [C1] J. Cong, Y. Fan, X. Yang, and Z. Zhang, Architecture and Synthesis for Multi-Cycle Communication, International Symposium on Physical Design (ISPD), Apr. 2003. (Invited Paper)