All News

2017

  • Aug 2017: Paper on using intra-core loop-task accelerators to improve the productivity and performance of task-based parallel programs was accepted to the 50th ACM/IEEE Int'l Symp. on Microarchitecture (MICRO'17)
  • Aug 2017: Paper on cross-layer workload characterization of meta-tracing JIT VMs was accepted to the IEEE Int'l Symp. on Workload Characterization (IISWC'17)
  • Jun 2012: Research group attended the 44th ACM/IEEE Int'l Symp. on Computer Architecture (ISCA'17) in Toronto, Canada
  • Jun 2017: Invited to be a visiting fellow at Clare Hall College and a visiting scholar at the Computer Laboratory at the University of Cambridge, UK during Spring/Summer of 2018
  • May 2017: Presentation on our Celerity system-on-chip (in collaboration with UCSD and University of Michigan) was accepted to the 29th ACM/IEEE Symp. on High-Performance Chips (HOTCHIPS'17)
  • May 2017: Ian Thompson, Mohammad Dohadwala, James Talmage, and Baturay Turkmen successfully completed their MEng design projects and graduated. Ian is heading to Green Hills Software, Mohammad is heading to Hyperloop, James is heading to Cavium, and Turkmen is heading to Intel – Congratulations!
  • May 2017: Taped out the Celerity system-on-chip: a 5x5mm 350M-transistor chip in TSMC 16nm designed and implemented by a large team of over 20 students and faculty from UC San Diego, University of Michigan, and Cornell as part of the DARPA Circuit Realization At Faster Timescales (CRAFT) program. The chip includes a fully synthesizable PLL, digital LDO, five modified Chisel-generated RISC-V Rocket cores, a 496-core RISC-V tiled manycore processor, tightly integrated Rocket-to-manycore communication channels, complex HLS-generated BNN (binarized neural network) accelerator, manycore-to-BNN high-speed links, sleep-mode 10-core manycore, top-level bus interconnect, high-speed source-synchronous off-chip I/O, and a custom flip-chip package. Cornell led the Rocket+BNN accelerator logical/physical design and also made key contributions to the top-level logical/physical integration and design/verification methodology.
  • May 2017: Gave guest lecture in ENGRI 1210 The Computing Technology Inside Your Smartphone on Recent Trends and Applications in Computer Engineering
  • May 2017: Research group celebrated with our end-of-the-semester barbecue
  • Mar 2017: Research group moved to the new home of the Computer Systems Laboratory in 471 Rhodes Hall. The space was designed by LEVENBETTS, a leading architecture firm from NYC, to facilitate a sense of community, encourage collaboration, support healthy living, and balance the multi-dimensional aspect of academia. The space includes new Ph.D. offices, lounge space, breakout rooms, and a state-of-the-art hardware prototyping research lab.
  • Jan 2017: Ji Kim wins the ECE Outstanding Ph.D. Thesis Award for his thesis titled "Software/Hardware Co-Design to Improve Productivity, Portability, and Performance of Loop-Task Parallel Applications" – Congratulations!
  • Jan 2017: Course website for ECE 5745 Complex Digital ASIC Design now online

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