Current Teaching

ECE 4750 / CS 4420 Computer Architecture

Fall 2010–2016 (Course Webpage)

This course provides a strong foundation for understanding modern computer system architecture and for designing future systems. The course is structured around the three primary building blocks of general-purpose computing systems: processors, memories, and networks. The first half of the course focuses on the fundamentals of each building block and will enable students to understand how these three building blocks can be integrated to build a simple multicore system. Topics include processor microcoding and pipelining; single-core and multi-core cache microarchitecture; and network topology, routing, and flow control. The second half of the course delves into more advanced techniques related to processors and memories and will enable students to understand sophisticated, modern multicore systems. Topics include superscalar execution, branch prediction, out-of-order execution, register renaming, memory disambiguation, VLIW processors, vector processors, multithreaded processors, address translation and protection, virtual memory, synchronization, consistency, coherence, and advanced cache microarchitecture. Students will learn how to evaluate design decisions in the context of past, current, and future application requirements and technology constraints. This course includes a significant project decomposed into five lab assignments. Throughout the semester, students will gradually design, implement, test, and evaluate a simple multicore system capable of running real parallel applications at the register-transfer level.

ECE 5745 Complex Digital ASIC Design

Spring 2012–2013, 2015–2017 (Course Webpage)

This course focuses on the principles and practices involved in the design, implementation, testing, and evaluation of complex standard-cell ASIC chips using automated state-of-the-art CAD tools. Topics include hardware description languages; CMOS logic, state, and interconnect fundamentals; chip design methodologies; automated cell-based design; CAD algorithms; details of accurately modeling ASIC delay, energy, and area; robustness issues; testing, verification, and debugging; power distribution and clocking; packaging and I/O. The course includes a six-week open-ended project where small groups of students design, implement, test, and evaluate an interesting technique in computer architecture using functional-, microarchitectural-, register-transfer-, and layout-level modeling.

ECE 5970 Special Topics: Chip-Level Interconnection Networks

Spring 2010 (Course Webpage)

Today's embedded, network, graphics, and server processors already contain tens to hundreds of cores integrated onto just a few chips, and this number will surely increase with future scaling. Chip-level interconnection networks, which connect cores on the same or different chips to each other and to main memory, are becoming a critical design component in terms of performance, power consumption, and programmer productivity. This course explores the underlying principles and the practical implementation issues for such networks. Topics include network topology, routing algorithms, flow-control strategies, router microarchitecture, performance analysis, and emerging physical technology issues. The course includes a mix of lectures and student-led discussion of both classic and modern research papers in the field. In the latter portion of the course, students work in small groups to design, implement, and evaluate an interesting research idea related to chip-level interconnection networks.