Cornell University
School of Electrical and Computer Engineering
ECE 4750 / CS 4420 / ECE 5740
Computer Architecture
Fall 2024
Prof. Anne Bracy
Mon/Wed @ 2:55–4:10pm • Gates G01
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Lecture Handouts
- Lecture 1: Course Overview (Next Steps after First Lecture)
- T01: Processor Concepts (notes) (problems)
- T02: Processor Microarchitecture (notes) (problems)
- T03: Memory Concepts (notes) (problems)
- T04: Memory Microarchitecture (notes) (problems)
- T05: Integrating Processors and Memories (notes) (problems)
- T06: Advanced Processors – Superscalar Execution (notes) (problems)
- T07: Advanced Processors – Out of Order Execution (notes) (problems)
- T08: Advanced Processors – Register Renaming (notes) (problems)
- T09: Advanced Processors – Memory Disambiguation
(notes, 4-up notes)
(notes we won't have time to look at, problems we won't have time to solve) - T10: Sidechannels, Meltdown, and Spectre, Oh My!
(notes, 4-up notes)
Lab Handouts
- Lab Assignment Logistics
- Lab 1: Iterative Integer Multiplier
- Lab 2: Pipelined Processor
- Lab 3: Blocking Cache
- Lab 4: Single-Core and Multi-Core Systems
Section Handouts
- Section 1: Linux Development Environment (github)
- Section 2: RTL Design with Verilog (github)
- Section 3: RTL Testing (github)
- Section 4: Lab 2 Head Start (github)
- Section 5: Pipelining Diagram Common Mistakes
- Section 6: Problem-Based Learning on Processor (solutions)
- [10/18] - Section 7: Lab 2 Extra Office Hour
- [10/25] - Section 8: Lab 3 Head Start (github)
- [11/01] - Section 9: Memory Random Testing and Queues
- [11/08] - Section 10: Lab 4 Head Start (was Section 11 previously, so still called 11 on the page)
- [11/15] - Section 11: Integrating Processors and Memories (solutions)
- [11/22] - Section 12: Networks