Lecture Handouts

• Lecture 1: Course Overview
• T01: Processor Concepts (notes) (problems)
• T02: Processor Microarchitecture (notes) (problems)
• T03: Memory Concepts (notes) (problems)
• Virtual Memory (slides)
• T04: Memory Microarchitecture (notes) (problems)
• T05: Integrating Processors and Memories (notes) (problems)
• T06: Advanced Processors – Superscalar Execution (notes) (problems)
• T07: Advanced Processors – Out of Order Execution (notes) (problems)

Lab Handouts

• Lab Assignment Logistics
• Lab 1: Iterative Integer Multiplier
• Lab 2: Pipelined Processor
• Lab 3: Blocking Cache
• Lab 4: Single-Core and Multi-Core Systems

Section Handouts

• Section 1: RTL Design with Verilog (github)
• Section 2: RTL Testing (github)
• Section 3: Lab 2 Head Start (github)
• Section 4: Pipelining Diagrams (handout, common mistakes)
• Section 5: Bug Hunt!
• Section 6: Lab 3 Head Start
• Section 7: Problem-Based Learning on Processor (soln)
• Section 8: Memory Random Testing and Queues
• Section 9: Lab 4 Head Start

Other Helpful Handouts

• Tiny RISC-V Instruction Set Specification
• Verilog RTL Usage Rules
• Cross-compile a simple C program for RISC-V

Tutorial Handouts

For those of you new to Cornell ECE, please look over Tutorial 0 to learn how to access the eductional ECE servers used in this course. We assume that everyone is familiar with using the command line and git. If this is not the case, please complete Tutorials 1 and 2 below to bring yourself up to speed.
• Tutorial 0: ECE Linux Server Remote Access
• Tutorial 1: Linux Command Line Basics
• Tutorial 2: Using Git
• Tutorial 3: Verilog Hardware Description Language (github)