ECE 5740 Readings

1. Asanovic and Patterson: Instruction Sets Should Be Free: The Case for RISC-V, 2014 (2 pages) [ pdf ]
2. William A. Wulf: Compilers and Computer Architecture, 1981 (7 pages) [ pdf ]
   
3. Colwell, Hitchcock, Jensen, Brinkley Sprunt, and Kollar: Instruction Sets and Beyond: Computers, Complexity, and Controversy, IEEE, 1985 (11 pages) [ pdf ]
4. S. Belayneh and D. Kaeli: A Discussion on Non-Blocking/Lockup-Free Caches, ACM SIGARCH Computer Architecture News, 24(3):18–25, Jun. 1996. (8 pages) [pdf]
5. Kenneth C. Yeager: The MIPS R10000 Superscalar Microprocessor, IEEE MICRO, Jun. 1996. (13 pages, but only ~10 required) [pdf, pdf marked to show out-of-scope paragraphs available on canvas]
   (short quiz not yet available)

Reading Materials

There are a variety of ways students can gain access to the required reading materials including: purchasing the books; using the hard copies in Uris Library; using the free online e-book available to Cornell students for Hennessy & Patterson, Harris & Harris, and Dally & Towles; and/or downloading materials from Canvas.

• J.L. Hennessy and D.A. Patterson. Computer Architecture: A Quantitative Approach, 5th edition. Morgan Kaufmann, 2012. [ library | amazon | ch1/pdf ]
• D.M. Harris and S.L. Harris. Digital Design and Computer Architecture, 2nd edition. Morgan Kaufmann, 2012. [ library | amazon ]
• M. Johnson. Superscalar Microprocessor Design. Prentice Hall, 1991. (Chapters 1, 2) [ library | amazon | pdf ]
• J. Silc, B. Robic, and T. Ungerer. Processor Architecture: From Dataflow to Superscalar and Beyond. Springer, 1999. (Chapter 4) [ library | amazon | pdf ]
• J.P. Shen and M.H. Lipasti. Modern Processor Design: Fundamentals of Superscalar Processors. McGraw-Hill Higher Education, 2004. (Chapter 5) [ library | amazon | pdf ]
• D.J. Sorin, M.D. Hill, and D.A. Wood. A Primer on Memory Consistency and Cache Coherence. Morgan & Claypool Synthesis Lectures, 2011. (Chapters 1–7) [ library | amazon | pdf ]
• W.J. Dally and B. Towles. Principles and Practices of Interconnection Networks. Morgan Kaufmann, 2004. (Chapters 1–5) [ library | amazon | pdf ]

Reading Assignments

Students are expected to complete all of the assigned reading according to the schedule below, although there is some flexibility. Some students may prefer to complete the readings before the corresponding lecture, while others may prefer to complete the readings after the corresponding lecture. Either strategy is acceptable.

Readings are marked with the following symbols:

• Harris and Harris, reviews material from prerequisite courses

• Hennessy and Patterson, optional, read if you have already read Harris and Harris in previous course

• Material not covered in prerequisite courses

Course Overview

• Hennessy and Patterson: Ch. 1 (60 pages)

Topic 1: Fundamental Processor Concepts

• Harris and Harris: Ch. 6, Ch. 7.1–7.3 (72 pages)
• Asanovic and Patterson: Instruction Sets Should Be Free: The Case for RISC-V, 2014 (2 pages) [ pdf ]

• Hennessy and Patterson: App. A (47 pages)

Topic 2: Fundamental Processor Microarchitecture

• Harris and Harris: Ch. 7.4 (20 pages)
• [optional: presents an alternative to hardwired control units for an FSM processor]
  Smotherman: A Brief History of Microprogramming, 2010 (27 pages) [ link ]
• Hennessy and Patterson: App. C.1–C.4 (51 pages)

Topic 3: Fundamental Memory Concepts

• Harris and Harris: Ch. 8.1–8.3 (20 pages)
• Hennessy and Patterson: App. B.4–B.5 (17 pages)
• Hennessy and Patterson: Ch. 2.4–2.6 (20 pages)

• Hennessy and Patterson: App. B.1–B.3 (39 pages)

Topic 4: Fundamental Memory Microarchitecture

• No readings

Topic 5: Integrating Processors and Cache Memories

• Heinrich: MIPS R4000 Microprocessor User's Manual, 1994 (some Ch. 3–4) [ pdf ]

Topic 6: Advanced Processors -- Superscalar Execution

• Silc, Robic, and Ungerer: Ch. 4–4.2 (8 pages)

Topic 7: Advanced Procesors -- Out-of-Order Execution

• Johnson: Ch. 2 (16 pages)
• Silc, Robic, and Ungerer: Ch. 4.4–4.8 (13 pages)

• Hennessy and Patterson: Ch. 3–3.11 (76 pages)

Topic 8: Advanced Procesors -- Register Renaming

• Shen and Lipasti: Ch. 5.2 (30 pages)

Topic 9: Advanced Procesors -- Memory Disambiguation

• Shen and Lipasti: Ch. 5.3 (13 pages)

Topic 10: Advanced Procesors -- Branch Prediction

• Silc, Robic, and Ungerer: Ch. 4.3 (21 pages)
• Shen and Lipasti: Ch. 5.1 (20 pages)

Topic 11: Advanced Procesors -- Speculative Execution

• No readings

Extra Topic 1: VLIW Processors

• Hennessy and Patterson: Ch. 3.2, 3.7, App. H.1–3 (32 pages)

Extra Topic 2: SIMD Processors

• Hennessy and Patterson: 4–4.6 (60 pages)

Extra Topic 3: Multithreaded Processors

• Hennessy and Patterson: Ch. 3.12 (10 pages)

Optional Reading for Architecture Case-Studies

• classic IO superscalar: Edmondson, Alpha 21164, IEEE Micro, 1995 [ pdf ]
• classic OOO superscalar: Yeager, MIPS R10000, IEEE Micro, 1996 [ pdf ]
• classic OOO superscalar: Kessler, Alpha 21264, IEEE Micro, 1996 [ pdf ]
• modern IO superscalar: Williamson, ARM Cortex-A8, Unique Chips and Systems, CRC Press, 2008 [ pdf ]
• modern OOO superscalar: Kanter, Intel's Haswell, Real World Tech, 2012 [ link ]
• modern OOO superscalar: Kanter, Intel Haswell-EX, Microprocessor Report, 2015 [ pdf ]
• modern OOO superscalar: Kanter, Intel Skylake, Microprocessor Report, 2015 [ pdf ]
• modern OOO superscalar: Kanter, AMD Zen, Microprocessor Report, 2016 [ pdf ]
• modern OOO superscalar: Halfhill, IBM Power9, Microprocessor Report, 2016 [ pdf ]
• modern OOO superscalar+SIMD: Kanter, Intel Knights Landing, Microprocessor Report, 2015 [ pdf ]
• modern OOO superscalar: Gwennap, Intel Golden Cove, Microprocessor Report, 2021 [ pdf ]
• modern OOO superscalar: Intel Golden Cove, Online Blog Post [ link ]