Online and Computing Resources

(git links coming soon)

• Canvas Learning Management System
• Ed Discussion Forums

Morgan & Claypool Synthesis Lectures

Morgan & Claypool publish a series of synthesis lectures in computer architecture, where each "lecture" is really a short book. These lectures are authored by some of the leading experts in computer architecture and serve as excellent surveys on many of the topics we cover in the course. All lectures are freely available to Cornell students on campus. Some of the more relevant synthesis lectures are listed below.

• Synthesis Lectures on Computer Architecture

• Computer Architecture Techniques for Power-Efficiency
• Multithreading Architecture
• The Memory System: You Can't Avoid It, You Can't Ignore It, You Can't Fake It
• A Primer on Hardware Prefetching
• Multi-Core Cache Hierarchies
• A Primer on Memory Consistency and Cache Coherence
• Shared-Memory Synchronization
• Transactional Memory
• High Performance Datacenter Networks: Architectures, Algorithms, and Opportunities
• Single-Instruction Multiple-Data Execution

Microprocessor Report

The Linley Group publishes the Microprocessor Report (MPR), a technical newsletter that provides in-depth analysis of high-performance processors in industry. MPR often provides detailed descriptions of the most recent chips from Intel, AMD, Oracle, NVIDIA, Cavium, and others. All MPR articles are freely available to Cornell students on campus. There is also a free email newsletter that provides short summaries and links to recently posted articles.

• Microprocessor Report
• Microprocess Report Newsletter

Agner Fog's Software Optimization Manuals

Agner Fog is a professor at the Technical University of Denmark, and he maintains one of the most remarkable and up-to-date collections of software optimization manuals for the x86 and x86-64 family microprocessors. The following five manuals describe: optimization tips for C++ and assembly language; details about the microarchitecture and instruction timings of most Intel, AMD and VIA processors; and details about different compilers and calling conventions. I highly recommend browsing through the Microarchitecture Optimization Guide; it has tremendous detail about the processor and memory systems in recent x86 processors and is a wonderful resource for computer architects.

• Manual 1: C++ Optimization Guide
• Manual 2: x86 Assembly Optimization Guide
• Manual 3: x86 Microarchitecture Optimization Guide
• Manual 4: x86 Instruction Tables
• Manual 5: C++ Calling Conventions

RISC-V Resources

• K. Asanovic and D. Patterson. Instruction Sets Should Be Free: The Case for RISC-V UC Berkeley Technical Report No. UCB/EECS-2014-146, August 6, 2014. [ pdf ]
• A. Waterman, Y. Lee, D. Patterson, K. Asanovic. The RISC-V Instruction Set Manual, Volume I: User-Level ISA. Version 2.1. May 31, 2016. [ pdf ]
• A. Waterman, Y. Lee, R. Avizienis, D. Patterson, K. Asanovic. The RISC-V Instruction Set Manual, Volume II: Privileged Architecture. Version 1.9. July 8, 2016. [ pdf ]
• D. Kanter. RISC-V Offers Simple, Modular ISA. Microprocessor Report, The Linley Group, March 28, 2016. [ pdf ]
• RISC-V Reference Card, RISC-V Foundation, 2015. [ pdf ]
• RISC-V Foundation Website

Verilog Coding Resources

• S. Palnitkar. Verilog HDL: A Guide to Digital Design and Synthesis, 2nd edition. Prentice Hall, 2003. [ amazon ]
• S. Sutherland, S. Davidmann, and P. Flake. SystemVerilog for Design: A Guide to Using SystemVerilog for Hardware Design and Modeling, 2nd edition. Spring, 2006. [ amazon ]
• C. Spear and G. Tumbush. SystemVerilog for Verification: A Guide to Learning the Testbench Language Features, 3rd edition. Spring, 2012. [ library | amazon | ch1/pdf ]
• S. Sutherland. The IEEE Verilog 1364-2001 Standard: What's New, and Why You Need It, Int'l HDL Conference and Exhibition, 2000. [ pdf ]
• C.E. Cummings. New Verilog-2001 Techniques for Creating Parameterized Models, Int'l HDL Conference and Exhibition, 2002. [ link | pdf ]
• S. Sutherland. Verilog HDL Quick Reference Guide (Verilog-2001), Sutherland HDL, 2001. [ pdf ]
• C.E. Cummings. Nonblocking Assignments in Verilog Synthesis, Coding Styles That Kill! Synopsys Users Group, San Jose, 2000. [ link | pdf ]
• D. Mills and C.E. Cummings. RTL Coding Styles That Yeild Simulation and Synthesis Mismatches, Snyopsys Users Group, San Jose, 1999. [ link | pdf ]
• S. Sutherland. I'm Still in Love With My X! Design and Verification Conference (DVCon), 2013. [ link | pdf ]
• M. Turpin. The Dangers of Living with an X (bugs hidden in your Verilog), ARM Ltd., 2003. [ pdf ]

Verilog Standards

• Verilog IEEE Standard 1364-1995
• Verilog IEEE Standard 1364-2001
• SystemVerilog 3.1a Language Reference Manual

MIPS32 Resources

• D. Sweetman. See MIPS Run Linux, 2nd edition. Morgan Kaufmann, 2006. [ library | amazon ]
• MIPS32 Architecture for Programmers, Volume I-A: Introduction to the MIPS32 Architecture. MIPS Technologies, Inc, 2013. [ pdf ]
• MIPS32 Architecture for Programmers, Volume II-A: The MIPS32 Instruction Set. MIPS Technologies, Inc, 2013. [ pdf ]
• MIPS32 Architecture for Programmers, Volume III: The MIPS32 and microMIPS32 Privileged Resource Architecture. MIPS Technologies, Inc, 2013. [ pdf ]
• MIPS32 Instruction Set Quick Reference, MIPS Technologies, Inc, 2008. [ pdf ]

Latency-Insensitive Interfaces

• C. Fletcher. EECS150: Interfaces: "FIFO" (a.k.a Ready/Valid). UC Berkeley, 2009. [ pdf ]
• G. Gibeling. GateLib: FIFO Interface. UC Berkeley, 2010. [ pdf ]

Open-Source Tools

• Git Distributed Version Control System
• Verilator Verilog Simulator
• Icarus Verilog Simulator
• GTKWave Waveform Viewer
• Inkscape Vector Graphics Editor
• Geany GUI-Based Text Editor
• Nano Text Editor
• Emacs Text Editor
• VIM Text Editor
• Keystrokes for Nano, Emacs, Vim