Miscellaneous Handouts and Links

• Zoom Meeting Information
• GitHub Username Signup
• Lab Group Signup
• Course Syllabus
• Next Steps after First Lecture
• Transitioning from PyMTL2 to PyMTL3
• PyMTL3 Overview Video
• PyMTL3 Demonstration Video (github)
• PyMTL3 RTL Usage Rules
• Verilog RTL Usage Rules
• Tiny RISC-V Instruction Set Specification
• Linux, Git, PyMTL, Verilog Cheat Sheet
• Project Ideas
• Project Meeting Schedule
• Project Report Assessment Rubric

Lecture Handouts

• Course Overview (notes)
• Topic 1: Hardware Description Languages (notes)
• Topic 2: CMOS Devices (notes)
• Topic 3: CMOS Circuits (notes)
• Topic 4: Full-Custom Design Methodology (activity, notes)
• Topic 5: Automated Design Methodologies (activity1, activity2, activity3, notes)
• Topic 6: Closing the Gap Between ASIC and Custom (notes)
• Topic 7: Packaging, Power Distribution, Clocking, and I/O
• Topic 8: Testing and Verification
• Topic 9: CMOS Combinational Logic (notes)
• Topic 10: CMOS Sequential State (notes)
• Topic 11: CMOS Interconnect (notes, video)
• Topic 12: Synthesis Algorithms (notes,activity1,activity2)
• Topic 13: Physical Design Automation Algorithms (notes)

Tutorials

• Tutorial 0: Remote Access to ecelinux
• Tutorial 1: Linux Development Environment
• Tutorial 2: Git Distributed Version Control System (github)
• Tutorial 3: PyMTL3 Hardware Modeling Framework (github)
• Tutorial 4: Verilog Hardware Description Language (github)
• Tutorial 5: Synopsys/Cadence ASIC Tools (github)
• Tutorial 6: PyHFlow Automated ASIC Flow (github)
• Tutorial 8: SRAM Generators (github)
• Tutorial 9: TinyRV2 Accelerators (github)
• Tutorial 10: SPICE Simulation (github)

Midterm Preparation

• Midterm Example Appendix
• Practice Problem 1 (solutions)
• Practice Problem 2 (solutions)

Lab Handouts

• Lab Assignment Logistics
• Lab 1: Pipelined Integer Multiplier
• Lab 2: Sorting Accelerator (results)