Christopher Batten
Associate Professor
Computer Systems Laboratory
School of Electrical and Computer Engineering
College of Engineering
Cornell University
office: 323 Rhodes Hall, Ithaca, NY 14853
phone: (607) 255-2672
email: cbatten cornell edu
I am an Associate Professor of Electrical and Computer Engineering and a graduate field member of Computer Science at Cornell University. My research group is part of the Computer Systems Laboratory, and we broadly work on energy-efficient parallel computer architecture for both high-performance and embedded applications. I am also interested in parallel programming methodologies, hardware specialization, interconnection networks, VLSI chip-design methodologies, and the intersection between computer architecture and future emerging technologies. Building prototype systems is an integral part of my research, as this is one of the best ways to validate assumptions, gain intuition about physical design issues, and provide platforms for future software research.
My research has been recognized with several awards including a Cornell Engineering Research Excellence Award (2015), an AFOSR Young Investigator Program award (2015), an Intel Early Career Faculty Honor Program award (2013), an NSF CAREER award (2012), a DARPA Young Faculty Award (2012), and an IEEE Micro Top Picks selection (2004). My teaching has been recognized with the Ruth and Joel Spira Award for Excellence in Teaching (2016), two Michael Tien '72 Excellence in Teaching Awards (2013,2017), and a James M. and Marsha D. McCormick Award for Outstanding Advising of First-Year Engineering Students (2013).
In 2018, I was a Visiting Scholar at the Computer Laboratory at the University of Cambridge, UK and a Visiting Fellow at Clare Hall also in Cambridge, UK. Prior to joining Cornell University, I received my Ph.D. in Electrical Engineering and Computer Science from the Massachusetts Institute of Technology. From 2007 to 2009, I was a visiting scholar in the Parallel Computing Laboratory at the University of California at Berkeley; I received an M.Phil. in Engineering as a Churchill Scholar at the University of Cambridge in 2000, and received a B.S. in Electrical Engineering as a Jefferson Scholar at the University of Virginia in 1999.
Recent News
- Nov 2020: Paper on CAPE, a content-addressable processing engine, (in collaboration with Prof. Martinez, Prof. Naryanan at Penn State, and their students) accepted to the 27th IEEE Int'l Symp. on High-Performance Computer Architecture (HPCA'21)
- Nov 2020: Paper on ultra-elastic CGRAs for irregular loop specialization accepted to the 27th IEEE Int'l Symp. on High-Performance Computer Architecture (HPCA'21)
- Nov 2020: Invited to present our vision for a new era of open-source system-on-chip design, using our work on PyMTL3 and Celerity as case studies, at the Electrical and Systems Engineering Departmental Seminar at the University of Pennsylvania, PA
- Nov 2020: Shunning Jiang presented our work-in-progress on implementing a universal butterfly transform accelerator generator in PyMTL3 and Moyang Wang presented our work-on-progress on implementing software-centric cache coherence in scalable manyocore architectures at the ADA SRC JUMP center annual symposium
- Oct 2020: Khalid Al-Hawaj presented our work exploring bit-serial vs. bit-parallel vector accelerators using in-situ processing-in-SRAM at the IEEE Int'l Symp. on Circuits and Systems (ISCAS'20) held virtually this year (video)
- Oct 2020: Invited to present our work on improving the performance and efficiency of deep learning recommender systems using PyTorch and RISC-V manycore accelerators at the Facebook AI Systems Faculty Summit
- Sep 2020: Co-organized with Michael Taylor (UW) a special session titled Unlock the NoC: Transforming NoC Research with Physical Design Awareness at the 14th ACM/IEEE Int'l Symp. on Networks-on-Chip (NOCS'20) held virtually this year; Yanghui Ou presented our work on implementing low-diameter on-chip networks for manycore processors using a tiled physical design methodology (video)
- Sep 2020: Shunning Jiang presented our work on PyMTL3 and Moyang Wang presented our work on heterogeneous cache coherence at SRC TECHCON 2020
- Aug 2019: Course website for ECE 2400 / ENGRD 2140 Computer Systems Programming now online
- Aug 2020: Paper on implementing low-diameter on-chip networks for manycore processors using a tiled physical design methodology invited for presentation at the 14th ACM/IEEE Int'l Symp. on Networks-on-Chip (NOCS'20)
- Jul 2020: Invited to present work on PyMTL3 for FPGA accelerator design at Xilinx
- Jul 2020: Appointed to serve on the editorial board of IEEE Micro as an Associate Editor
- Jul 2020: National Science Foundation (NSF) proposal to explore ephemeral vector engines using in-situ processing-in-SRAM is funded
- Jul 2020: Paper on PyMTL3, a Python framework for open-source hardware modeling, generation, simulation, and verification published in IEEE Micro
- Jun 2020: Juan Albrecht, Leandro Dorta Duque, and Raymond Yang completed their MEng design projects and graduated. Jaun is heading to Apple, Leo is heading to Intel, and Juan is heading to Marvell – Congratulations!
- Jun 2020: Moyang Wang presented our work on efficiently supporting dynamic task parallelism on heterogeneous cache-coherent systems at the ACM/IEEE Int'l Symp. on Computer Architecture (ISCA'20) held virtually this year (video)
- May 2020: Presented our work on PyMTL3 including a demo at CHIPKIT: 2nd Tutorial on Agile Research Test Chips held virtually this year (video1,video2)
- May 2020: Shunning Jiang and Tuan Ta prepared a demonstration video announcing our official PyMTL3 release as part of the ADA SRC JUMP center annual symposium
- May 2020: Most recent issue of ECE Connections magazine includes an article about our work as part of a large team exploring new materials, devices, circuits, and architectures for processing-in-memory and an article about the Computer Systems Laboratory's efforts to build a collaborative research community
- May 2020: Gave guest lecture in ENGRI 1210 The Computing Technology Inside Your Smartphone on Recent Trends in Computer Engineering
- Apr 2020: BRG is now 100% virtual but is still making great progress on all of our reseach projects including a DARPA POSH CIFER 14nm tapeout, BRGTC3 TSMC 180nm tapeout, DARPA SDH Hammerblade Pytorch port, PyMTL3 release, and accelerators using in-situ processing-in-SRAM
- Mar 2020: Paper on efficiently supporting dynamic task parallelism on heterogeneous cache-coherent systems accepted to the 47th ACM/IEEE Int'l Symp. on Computer Architecture (ISCA'20)
- Mar 2020: Invited to serve on the program committee for the 53rd ACM/IEEE Int'l Symp. on Microarchitecture (MICRO'20)
- Mar 2020: Paper exploring bit-serial vs. bit-parallel vector accelerators using in-situ processing-in-SRAM accepted to the IEEE Int'l Symp. on Circuits and Systems (ISCAS'20)
- Feb 2020: Facebook proposal to explore hardware/software co-design for deep learning recommender systems (with our collaborator Prof. Michael Taylor at the University of Washington) as part of the Systems for Machine Learning program is funded
- Feb 2020: Lin Cheng presented our work on type freezing, a new technique to exploit attribtue type monomorphism in tracing JIT compilers, at the ACM/IEEE Int'l Symp. on Code Generation and Optimization (CGO'20) in San Diego, CA
- Jan 2020: Paper exploring bit-serial vs. bit-parallel vector accelerators using in-situ processing-in-SRAM accepted to the IEEE Int'l Symp. on Circuits and Systems (ISCAS'20)
- Jan 2020: Course website for ECE 5745 Complex Digital ASIC Design now online
- Jan 2020: Attended the DARPA IDEA/POSH integration excercise in Salt Lake City, UT to collaboratively work on our Python-based on-chip network generator and RTL testing framework
- Jan 2020: JUMP ADA Center seed proposals to explore using PyMTL to implement homomorphic encryption accelerators and integrating Spandex into the HammerBlade SoC are funded
- Dec 2019: Cheng Tan is finishing his post-doc in the Batten Research Group and heading to be a Postdoctoral Associate at the Pacific Northwest National Laboratory – Congratulations!
- Dec 2019: Co-organized a coding sprint with Princeton University for our DARPA POSH project including collaborative hacking on our upcoming GF 12nm tapeout and a joint ski trip
- All News
Current Research Projects
- Programmable Accelerator-Based Architectures
- General-Purpose Graphics Processing Unit Microarchitecture
- Algorithm and Data-Structure Hardware Specialization
- Architecture and Circuit Co-Design for Integrated Voltage Regulation
- Python-Based Frameworks to Enable a Vertically Integrated Research Methodology
- FPGA/ASIC Prototyping
Current Teaching
Educational Outreach Activities
- ENGRG 1050 Engineering Seminar: Computer Engineering Hands-On Experience
- ENGRG 1060 Explorations in Engineering: Computer Engineering Unit
- Curie Academy 2014: Week-Long Design Experience
Research Group
- Dr. Shady Agwa (postdoc)
- Moyang Wang (MS/PhD)
- Shunning Jiang (MS/PhD)
- Khalid Al-Hawaj (MS/PhD)
- Tuan Ta (MS/PhD)
- Lin Cheng (MS/PhD)
- Yanghui Ou (MS/PhD)
- Peitian Pan (MS/PhD)
- Nick Cebry (MS/PhD)
- Kexin (Grace) Zheng (MEng)
- Rohan Agarwal (MEng)
- Kenneth Mao (Meng)
- Cameron Haire (BS)
- Jack Weber (BS)
- Angela Zou (BS)
- Ken Ho (BS)
- Krithik Ranjan (BS)
- Janice Wei (BS)
- Former Members
Research Sponsors
- National Science Foundation: SHF'20/'15, E2CDA'17, CRI'15/'11, XPS'13, EAGER'11, CAREER'12
- Defense Advanced Research Projects Agency: POSH'18, SDH'18, CRAFT'16, YFA'12,
- Air Force Office of Scientific Research: YIP'15
- Semiconductor Research Corporation: JUMP'18, E2CDA'17
- Intel Corporation: research funding and equipment donation
- Facebook: research funding
- NVIDIA: research funding and equipment donation
- Xilinx: research funding and CAD tool donation
- Cornell Engineering Learning Initiatives: undergraduate research funding
- Advanced Micro Devices: undergraduate research funding
- Synopsys: CAD tool donation
- ARM: physical IP donation
- GitHub, TravisCI, Codecov.io: hosted software donations
Professional Activities
- Conference PC Member: MICRO'20/'15, ISCA'17/'15/'13, SC'17/'16, HPCA'16
- Conference PC Member: IEEE Micro TopPicks'16, PPoPP'13, ASPLOS'11
- Conference External Reviewer: ISCA, ASPLOS, MICRO, HPCA, DAC, SIGMETRICS
- Conference Organizing Committee Member: HPCA'14
- Workshop PC Member: WDDD'16, GPGPU'16, NOPE'15, WDDD'15, GPGPU'14
- Workshop Co-Organizer: SIGARCH Visioning Workshop on Open and Agile HW Design, WARP'15, WINDS'10
- Tutorial Co-Organizer: PyMTL'19, PyMTL/Pydgin'15
- Associate Editor: IEEE Micro'20–22
- Journal Reviewer: IEEE Micro, CACM, JETCAS, TCAD, TVLSI, TACO, CAL, MICPRO, COMPUTER
- Book Reviewer: Morgan and Claypool Synthesis Lectures on Computer Architecture
- Member: IEEE Computer Society, ACM SIGARCH