Our research focus is on signal processing theory, algorithm development, and digital VLSI circuits and systems for signal and information processing applications requiring highest throughput, lowest latency, and best-in-class results. Our current focus is on low-precision massive multiple-input multiple-output (MIMO) wireless systems, approximate solvers for signal recovery from nonlinear measurements (including phase retrieval problems), analog-to-information (A2I) and analog-to-feature (A2F) converters for low-power classification and inference, as well as real-time image computational imaging. In all these fields, we develop hardware-friendly algorithms, perform a thorough theoretical analysis of the algorithms' performance and complexity, and implement corresponding digital VLSI circuits.

Realizing massive MIMO with approximate algorithms and low-complexity architectures


Massive (or large-scale) MIMO is an emerging wireless communication technology that builds upon the idea of having orders of magnitude more antennas at the base station (BS) compared to conventional (small-scale) MIMO systems, while serving tens of users simultaneously and in the same frequency band. This recent technology promises significant improvements in terms of spectral efficiency, link reliability, and coverage. Unfortunately, all these benefits come at the cost of significantly increased computational complexity at the BS for realistic antenna configurations. In particular, data detection in the uplink and precoding in the downlink, as well as impairment compensation, are expected to be among the most critical tasks in terms of complexity and power consumption. Our research aims at developing novel baseband processing algorithms that will enable the benefits of massive MIMO in practical systems at low cost and low power. To this end, we develop novel algorithms, provide corresponding theoretical performance guarantees, and integrate our solutions in ASICs and design FPGA prototypes. The image on the left shows the first data detector ASIC layout for a 3GPP-LTE-based 128-antenna, 8-user massive MIMO system achieving more than 3.8Gb/s.

Selected publications

M. Wu, C. Dick, J. R. Cavallaro, and C. Studer, "High-Throughput Data Detection for Massive MU-MIMO-OFDM using Coordinate Descent,” IEEE Transactions on Circuits and Systems I, Vol. 64, No. 12, Dec. 2016, (invited journal article; IEEE Xplore 19th most downloaded paper in Dec. 2016)
C. Studer and G. Durisi, "Quantized MU-MIMO-OFDM Uplink,” IEEE Transactions on Communications, Vol. 64, No. 6, pp. 2387-2399, Apr. 2016
M. Wu, Bei Yin, G. Wang, C. Dick, J. R. Cavallaro, and C. Studer, "Large-Scale MIMO Detection for 3GPP LTE: Algorithm and FPGA Implementation," IEEE Journal of Selected Topics in Signal Processing, Mar. 2014
C. Studer and Erik G. Larsson, "PAR-Aware Large-Scale Multi-User MIMO-OFDM Downlink," IEEE Journal on Selected Areas in Communications, Vol. 31, No. 2, pp. 303–313, Feb. 2013

Real-time approximate discrete programming


Discrete programming (DP) deals with optimization problems involving variables that range over a discrete (e.g., binary or integer-valued) solution space. DP is an important tool in a variety of applications including digital communications, operations research, and computer vision. While discrete programs are typically solved offline by sophisticated software using powerful computers, DP has recently emerged as an important tool in applications requiring real-time processing in embedded systems with stringent area, cost, and power constraints. Our research fuses optimization theory, numerical methods, and integrated circuit design to develop fast algorithms and suitable hardware architectures for real-time DP in embedded systems. Our focus is no real-time applications in communication systems, imaging and computer vision, and machine learning. The image on the left shows the first semidefinite relaxation (SDR) solver that has been in VLSI; the solver is called TASER and performs SDR-based data detection in multi-antenna systems with up to 64 users.

Selected publications

T. Goldstein and C. Studer, "PhaseMax: Convex Phase Retrieval via Basis Pursuit,” submitted to a journal, arXiv preprint: 1610.07531
O. Castañeda, T. Goldstein, and C. Studer, "Data Detection in Large Multi-Antenna Wireless Systems via Approximate Semidefinite Relaxation,” IEEE Transactions on Circuits and Systems I, Vol. 64, No. 12, Dec. 2016, (invited journal article)
S. Shah, A. Kumar, D. Jacobs, C. Studer, and T. Goldstein, "Biconvex Relaxation for Semidefinite Programming in Computer Vision," 14th European Conference on Computer Vision (ECCV), Oct. 2016

Analog-to-information (A2I) and analog-to-feature (A2F) conversion

Accelerated sparse signal dequantization ASIC

In a large number of communications and signal-processing applications, such as wide-band radio-frequency (RF) spectrum sensing or multi-channel signal acquisition, sensing or sampling signals at the Nyquist rate results in prohibitive data rates and requires power-inefficient and expensive analog-to-digital (ADC) converters. In recent years, advances in compressive sensing and sparse signal processing have shown that signals with low-dimensional structure (e.g., sparsity or low-rank) can be sampled and recovered well-below the Nyquist rate. The main idea is to jointly perform signal acquisition and dimensionality reduction, while preserving the signals' information. Such analog-to-information (A2I) converters enable inexpensive and energy-efficient ways of sampling of analog signals, while sophisticated recovery algorithms extract the information of interest. Most existing A2I solutions perform sampling using dedicated hardware but perform recovery off-line using expensive commodity hardware and computationally complex algorithms. In contrast, we explore novel integrated A2I converter designs that jointly consider sampling and recovery, which enables us to achieve low-latency information recovery at higher bandwidths, as well as novel ways to compensate for system impairments directly within the recovery circuitry. The image on the left shows a 28nm SOI implementation of a novel accelerated sparse signal dequantization (ASSD) engine for A2I-based 6GHz wideband spectrum sensing.

Selected publications

M. Pelissier and C. Studer, "Non-Uniform Wavelet Sampling for RF Analog-to-Information Conversion," submitted to a journal
C. Studer and R. G. Baraniuk, "Stable Restoration and Separation of Approximately Sparse Signals," Applied and Computational Harmonic Analysis, Vol. 37, pp. 12-32, Sep. 2014
D. Bellasi, L. Bettini, C. Benkeser, T. Burger, Q. Huang, and C. Studer, "Monolithic Compressive-Sensing Wideband Analog-to-Information Converter," IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Vol. 3, No. 4, pp. 552–565, Dec. 2013

Real-time image computational imaging

Fluorescence denoising example

Computational imaging is a fairly new field that fuses optics, imaging sensors, and computation to overcome the limitations of traditional imaging systems (e.g., photo or video cameras, microscopes, etc.). Computational imaging enables, for example, inexpensive light-field, high-speed, or hyperspectral imaging (or a combination thereof), which finds use in a large number of practical applications, ranging from consumer electronics to biology, physics, or defense applications. Unfortunately, computational imaging requires complex algorithms that operate on massive datasets, and is typically deployed in systems with stringent throughput and quality constraints. Existing systems perform the underlying algorithms off-line using expensive and power-inefficient general-purpose processors or graphics processing units (GPUs), which prohibits the use of this technology in portable (battery powered) and real-time imaging systems. To enable computational imaging in real-time systems, we develop new hardware-friendly algorithms that enable real-time processing using field-programmable gate arrays (FPGAs) or application-specific integrated circuits (ASICs). Our main focus is to develop a real-time computational imaging platform that overcomes the limitations of existing off-line prototypes. The image on the left shows a low-light denoising application using fluorescence microscopy; we are currently developing new algorithms and hardware designs that perform this denoising task in real-time on inexpensive FPGA platforms.

Selected publications

R. G. Baraniuk, T. Goldstein, A. C. Sankaranarayan, C. Studer, A. Veeraraghavan, and M. Wakin, "Compressive Video Sensing: Algorithms, architectures, and applications," IEEE Signal Processing Magazine, Vol. 34, No. 1, Jan. 2017, (feature article)
A. Sankaranarayanan, L. Xu, C. Studer, Y. Li, K. F. Kelly, and R. G. Baraniuk, "Video Compressive Sensing for Spatial Multiplexing Cameras using Motion-Flow Models,” SIAM Journal of Imaging Sciences, Vol. 8, No. 3, pp. 1489-1518, July 2015
S. Shah, T. Goldstein, and C. Studer, "Estimating Sparse Signals with Smooth Support via Convex Programming and Block Sparsity," IEEE Conference on Computer Vision and Pattern Recognition (CVPR), June 2016

The support of the following grants, funding agencies, and companies is gratefully acknowledged.

E2CDA: TYPE 1: Durable, Energy-Efficient, Pausable Processing in Polymorphic Memories (DEEP3M), National Science Foundation (NSF), EECS
NeTS: Small: Collaborative Research: BRICK: Breaking the I/O and Computation Bottlenecks in Massive MIMO Base Stations, National Science Foundation (NSF), CNS
CAREER: Hardware Accelerated Bayesian Inference via Approximate Message Passing: A Bottom-Up Approach, National Science Foundation (NSF), CCF
AitF: EXPL: Collaborative Research: Approximate Discrete Programming for Real-Time Systems, National Science Foundation (NSF), CCF
Collaborative Research: BAMM: Baseband Accelerators for Massive Multiple-Input Multiple-Output (MIMO) Technology, National Science Foundation (NSF), EECS
NVIDIA GPU Grant Program, Nvidia, Santa Clara, CA, USA
Xilinx University Program, Xilinx Inc., San Jose, CA, USA
TI University Program, Texas Instruments Inc., Dallas, TX, USA

In alphabetical order.