Zhiru Zhang
Professor

Computer Systems Laboratory
School of Electrical and Computer Engineering
College of Engineering
Cornell University

office: 320 Rhodes Hall, Ithaca, NY 14853
phone: (607) 255-5954
email: zhiruz -at- cornell.edu

Dr. Zhiru Zhang is a Professor in the School of Electrical and Computer Engineering at Cornell University and a member of the Computer Systems Laboratory. His current research investigates new algorithms, methodologies, and design automation tools for heterogeneous computing systems. Recent publications from his group focus on the topics of high-level synthesis (HLS), hardware specialization for machine learning, and programming models for software-defined FPGAs.

He is an IEEE Fellow and has been honored with the Intel Outstanding Researcher Award, AWS AI Amazon Research Award, Facebook Research Award, Google Faculty Research Award, DAC Under-40 Innovators Award, Rising Professional Achievement Award from the UCLA Henry Samueli School of Engineering and Applied Science, DARPA Young Faculty Award, IEEE CEDA Ernest S. Kuh Early Career Award, NSF CAREER Award, and Ross Freeman Award for Technical Innovation from Xilinx. He has won multiple Best Paper Awards from top conferences and journals, including ASPLOS (2025), ISPD (2025), FPGA (2024, 2022, 2021, 2019), AutoML (2024), FCCM (2018), ACM TODAES (2012), and Top Picks in Hardware and Embedded Security (2020). His papers on HLS scheduling and application-specific instruction-set processor (ASIP) compilation have been inducted into the ACM/SIGDA TCFPGA Hall of Fame for the classes of 2022 and 2023, respectively. On the teaching side, he received the Ruth and Joel Spira Award for Excellence in Teaching (2018) and twice the Michael Tien'72 Excellence in Teaching Award (2016, 2022), the highest recognition for teaching in the College of Engineering.

Prior to joining Cornell, he earned his Ph.D. in Computer Science from UCLA and co-founded AutoESL based on his dissertation research on HLS. AutoESL was acquired by Xilinx (now AMD), and its HLS tool evolved into Vivado HLS (now Vitis HLS), which is widely used for designing FPGA-based hardware accelerators. He also holds a B.S. in Computer Science from Peking University and an M.S. in Computer Science from UCLA.

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