Miscellaneous Handouts

• Course Syllabus
• Next Steps after First Lecture
• Tiny RISC-V Instruction Set Specification
• Lab Assignment Assessment Rubric
• PyMTL RTL Usage Rules
• Verilog RTL Usage Rules
• Linux, Git, PyMTL, Verilog Cheat Sheet

Lecture Handouts

• Course Overview (results from activities)
• T01: Fundamental Processor Concepts
• T02: Fundamental Processor Microarchitecture
• T03: Fundamental Memory Concepts
• T04: Fundamental Memory Microarchitecture
• T05: Integrating Processors and Memories
• T06: Fundamental Network Concepts
• T07: Fundamental Network Microarchitecture
• T08: Integrating Processors, Memories, and Networks
• T09: Advanced Processors – Superscalar Execution
• T10: Advanced Processors – Out-of-Order Execution (I2OE, I2OL, IO2E)
• T11: Advanced Processors – Register Renaming
• T12: Advanced Processors – Memory Disambiguation
• T13: Advanced Processors – Branch Prediction
• T14: Advanced Processors – Speculative Execution (extra)
• T15: Advanced Processors – VLIW Processors (extra)
• T16: Advanced Processors – SIMD Processors
• T17: Advanced Processors – Multithreaded Processors

Section Handouts

• PyMTL Hardware Modeling Framework
• Problem Based Learning: Pipelined Processors (sol)
• Common Mistakes in Pipeline Diagrams
• Using ASIC Flow to Quantify Cycle Time (critical path)
• Problem Based Learning: Cache Memories (sol)
• Problem Based Learning: Networks (sol)
• Example Architecture: Intel Skylake

Lab Handouts

• Lab 1: Iterative Integer Multiplier (dpath, ctrl)
• Lab 2: Pipelined Processor (dpath)
• Lab 3: Blocking Cache (dpath, ctrl)
• Lab 4: Ring Network (dpath, ctrl, alt)
• Lab 5: Multicore System (base, alt, cachenet, memnet, datacache)

Tutorials

• Tutorial 1: Linux Development Environment
• Tutorial 2: Git Distributed Version Control System (github)
• Tutorial 3: PyMTL Hardware Modeling Framework (github)
• Tutorial 4: Verilog Hardware Description Language (github)