Reading Materials

There are a variety of ways students can gain access to the required reading materials including: purchasing the books; purchasing the course packet; using the hard copy reserves in Uris Library; using the free online e-book available to Cornell students for Hennessy & Patterson, Harris & Harris, and Dally & Towles; and/or downloading specific excerpts from the course webpage using the username and password distributed in lecture.

• J.L. Hennessy and D.A. Patterson. Computer Architecture: A Quantitative Approach, 5th edition. Morgan Kaufmann, 2012. [ amazon | publisher | ch1/pdf | reserves | ebook ]
• D.M. Harris and S.L. Harris. Digital Design and Computer Architecture, 2nd edition. Morgan Kaufmann, 2012. [ amazon | reserves | ebook ]
• M. Johnson. Superscalar Microprocessor Design. Prentice Hall, 1991. (Chapters 1, 2 in course packet) [ amazon | pdf | reserves ]
• J. Silc, B. Robic, and T. Ungerer. Processor Architecture: From Dataflow to Superscalar and Beyond. Springer, 1999. (Chapter 4 in course packet) [ amazon | pdf | reserves ]
• J.P. Shen and M.H. Lipasti. Modern Processor Design: Fundamentals of Superscalar Processors. McGraw-Hill Higher Education, 2004. (Chapter 5 in course packet) [ amazon | pdf | reserves ]
• D.J. Sorin, M.D. Hill, and D.A. Wood. A Primer on Memory Consistency and Cache Coherence. Morgan & Claypool Synthesis Lectures, 2011. (Chapters 1–7 in course packet) [ amazon | publisher | pdf ]
• W.J. Dally and B. Towles. Principles and Practices of Interconection Networks. Morgan Kaufmann, 2004. (Chapters 1–5, 8–10, 12–14, 18, 23 in course packet) [ amazon | topo/pdf | reserves | ebook ]

Reading Assignments

Students are expected to complete all of the assigned reading according to the schedule below, although there is some flexibility. Some students may prefer to complete the readings before the corresponding lecture, while others may prefer to complete the readings after the corresponding lecture. Either strategy is acceptable.

Readings are marked with the following symbols:

• Harris and Harris, reviews material from prerequisite courses

• Hennessy and Patterson, optional, read if you have already read Harris and Harris in previous course

• Material not covered in prerequisite courses

Course Overview

• Hennessy and Patterson: Ch. 1 (60 pages)

T01: [FP] Fundamental Processor Concepts

• Harris and Harris: Ch. 6, Ch. 7.1–7.3 (72 pages)
• Asanovic and Patterson: Instruction Sets Should Be Free: The Case for RISC-V, 2014 (2 pages) [ pdf ]

• Hennessy and Patterson: App. A (47 pages)

T02: [FP] Fundamental Processor Microarchitecture

• Harris and Harris: Ch. 7.4 (20 pages)
• Smotherman: A Brief History of Microprogramming, 2010 (27 pages) [ link | pdf ]
• Hennessy and Patterson: App. C.1–C.4 (51 pages)

T03: [FM] Fundamental Memory Concepts

• Harris and Harris: Ch. 8.1–8.3 (20 pages)
• Hennessy and Patterson: App. B.4–B.5 (17 pages)
• Hennessy and Patterson: Ch. 2.4–2.6 (20 pages)

• Hennessy and Patterson: App. B.1–B.3 (39 pages)

T04: [FM] Fundamental Memory Microarchitecture

• No readings

T05: [FM] Integrating Processors and Cache Memories

• Heinrich: MIPS R4000 Microprocessor User's Manual, 1994 (some Ch. 3–4) [ pdf ]

T06: [FN] Fundamental Network Concepts

• Dally and Towles: Ch. 1.3–1.4, 2, 3–3.3, 4–4.3, 5–5.3 (57 pages)
• Dally and Towles: Ch. 8–8.4, 9.1, 10–10.2, 14–14.2.2 (31 pages)

T07: [FN] Fundamental Network Microarchitecture

• Dally and Towles: Ch. 12–12.3, 13.3 (20 pages)
• Dally and Towles: Ch. 18–18.4, 23–23.1.2 (17 pages)

T08: [FM] Integrating Processors, Cache Memories, and Networks

• No readings

T09: [AP] Superscalar Execution

• Silc, Robic, and Ungerer: Ch. 4–4.2 (8 pages)

T10: [AP] Out-of-Order Execution

• Johnson: Ch. 2 (16 pages)
• Silc, Robic, and Ungerer: Ch. 4.4–4.8 (13 pages)

• Hennessy and Patterson: Ch. 3–3.11 (76 pages)

T11: [AP] Register Renaming

• Shen and Lipasti: Ch. 5.2 (30 pages)

T12: [AP] Memory Disambiguation

• Shen and Lipasti: Ch. 5.3 (13 pages)

T13: [AP] Branch Prediction

• Silc, Robic, and Ungerer: Ch. 4.3 (21 pages)
• Shen and Lipasti: Ch. 5.1 (20 pages)

T14: [AP] Speculative Execution

• No readings

T15: [AP] VLIW Processors

• Hennessy and Patterson: Ch. 3.2, 3.7, App. H.1–3 (32 pages)

T16: [AP] SIMD Processors

• Hennessy and Patterson: 4–4.6 (60 pages)

T17: [AP] Multithreaded Processors

• Hennessy and Patterson: Ch. 3.12 (10 pages)

T18: [AM] Advanced Cache Microarchitecture

• Hennessy and Patterson: Ch. 2.1–2.2 (24 pages)

T19: [AM] Memory Consistency, Coherence, and Synchronization

• Sorin, Hill, and Wood: Ch. 1–3.7, 6–7.4 (53 pages)

Optional Reading for Architecture Case-Studies

• classic IO superscalar: Edmondson, Alpha 21164, IEEE Micro, 1995 [ pdf ]
• classic OOO superscalar: Yeager, MIPS R10000, IEEE Micro, 1996 [ pdf ]
• classic OOO superscalar: Kessler, Alpha 21264, IEEE Micro, 1996 [ pdf ]
• modern IO superscalar: Williamson, ARM Cortex-A8, Unique Chips and Systems, CRC Press, 2008 [ pdf ]
• modern OOO superscalar: Kanter, Intel's Haswell, Real World Tech, 2012 [ link ]
• modern OOO superscalar: Kanter, Intel Haswell-EX, Microprocessor Report, 2015 [ pdf ]
• modern OOO superscalar: Kanter, Intel Skylake, Microprocessor Report, 2015 [ pdf ]
• modern OOO superscalar: Kanter, AMD Zen, Microprocessor Report, 2016 [ pdf ]
• modern OOO superscalar: Halfhill, IBM Power9, Microprocessor Report, 2016 [ pdf ]
• modern OOO superscalar+SIMD: Kanter, Intel Knights Landing, Microprocessor Report, 2015 [ pdf ]