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David H. Albonesi

David H. Albonesi

Computer Systems Laboratory
School of Electrical and Computer Engineering
Cornell University
333 Rhodes Hall
Ithaca, NY 14853
(607) 254-5473
dha7 at

I joined the Computer Systems Laboratory in 2004 after eight years at the University of Rochester Before returning to graduate school to pursue an academic career, I spent ten years in the computer industry as a technical manager, lead architect, and chip designer.

My primary research focus for the last 20+ years is power-efficient computer architecture. Recent research contributions include scalable power management algorithms, dynamically adaptive computer architectures, accelerator architectures for deep neural networks, dynamic GPGPU power management, shared reconfigurable architectures for chip multiprocessors, architectures for accelerating human-computer interaction, and applications to energy-efficient smart buildings.

I am a Fellow of the IEEE, and received the National Science Foundation CAREER Award, three IEEE Micro Top Picks Awards, three IBM Faculty Awards, and the International Symposium on Microarchitecture Test of Time Award. I was General co-Chair of the 42nd International Symposium on Microarchitecture and Program Chair of the 42nd International Symposium on Computer Architecture. Currently I serve on the Editorial Board of IEEE Computer; past editorial service includes Editor-in-Chief of IEEE Micro.

In terms of teaching, I have received the Kenneth A. Goldman '71, Michael Tien '72, and Ralph S. Watts '72 College of Engineering Excellence in Teaching Awards; and the Ruth and Joel Spira Excellence in ECE Teaching Award (twice). In 2015, I created a MOOC, The Computing Technology Inside Your Smartphone, from a freshmen class. Subsequently, I turned that freshmen class into a flipped classroom. In addition to that course, I currently teach one for sophomores on digital design and computer organization.

More about me can be found in my CV.

Selected publications

CuttleSys: Data-Driven Resource Management for Interactive Services on Reconfigurable Multicores, N. Kulkarni et al., 53rd International Symposium on Microarchitecture, October 2020.

MatRaptor: A Sparse-Sparse Matrix Multiplication Accelerator Based on Row-Wise Product, N. Srivastava et al., 53rd International Symposium on Microarchitecture, October 2020.

Tensaurus: A Versatile Accelerator for Mixed Sparse-Dense Tensor Computations, N. Srivastava et al., 26th International Symposium on High-Performance Computer Architecture, February 2020.

T2S-Tensor: Productively Generating High-Performance Spatial Hardware for Dense Tensor Computations, N. Srivastava et al., 27th International Symposium on Field-Programmable Custom Computing Machines, April 2019.

DeepRecon: Dynamically Reconfigurable Architecture for Accelerating Deep Neural Networks, T. Rzayev, S. Moradi, D.H. Albonesi, and R. Manohar, International Joint Conference on Neural Networks, May 2017.

Toolbox for Exploration of Energy-Efficient Event Processors for Human-Computer Interaction, T. Rzayev, D.H. Albonesi, R. Manohar, F. Guimbretiere, and J. Kihm, International Symposium on Performance Analysis of Systems and Software, April 2017.

Dynamic GPGPU Power Management Using Adaptive Model Predictive Control, A. Majumdar, L. Piga, I. Paul, J.L. Greathouse, W. Huang, and D.H. Albonesi, 23rd International Symposium on High Performance Computer Architecture, February 2017.

Characterizing the Benefits and Limitations of Smart Building Meeting Room Scheduling, A. Majumdar, Z. Zhang, and D.H. Albonesi, 7th International Conference on Cyber-Physical Systems, April 2016.