Issued Patents
Building Power Management Systems, D.H. Albonesi, H. Chong, B. Hencey, and C.A. Shoemaker, U.S. Patent 10,371,405, issued 8/6/19.
Multi-Core Computer Processor Based on a Dynamic Core-Level Power
Management for Enhanced Overall Power Efficiency,
P. Patrica, A.M. Izraelevitz, D.H. Albonesi, and
C.A. Shoemaker, U.S. Patent 10,088,891, issued 10/2/18.
Performance Monitoring for New Phase Dynamic Optimization of
Instruction Dispatch Cluster Configuration, R. Balasubramonian,
S. Dwarkadas, and D.H. Albonesi, U.S. Patent 8,103,856, issued
January 24, 2012.
Adaptive Issue Queue for Reduced Power at High Performance,
A. Buyuktosunoglu, S. Schuster, D. Brooks, P. Bose, P. Cook, and
D.H. Albonesi, U.S. Patent 7,865,747, issued January 4, 2011.
Dynamic Data Dependence Tracking and its Application to Branch Prediction,
L. Chen, D. Albonesi, and S. Dropsho, U.S. Patent 7,571,302, issued August
4, 2009.
Multi-cluster Processor Operating Only Select Number of Clusters During Each
Phase Based on Program Statistic Monitored at Predetermined Intervals,
R. Balasubramonian, S. Dwarkadas, and D.H. Albonesi, U.S. Patent
7,490,220, issued February 10, 2009.
Multiple Clock Domain Microprocessor, D.H. Albonesi, G. Semeraro,
G. Magklis, M.L. Scott, R. Balasubramonian, and S. Dwarkadas,
U.S. Patent 7,089,443, issued August 8, 2006.
Multiple Clock Domain Microprocessor, D.H. Albonesi, G. Semeraro,
G. Magklis, M.L. Scott, R. Balasubramonian, and S. Dwarkadas,
U.S. Patent 7,739,537, issued March 26, 2006.
Memory Hierarchy Reconfiguration for Energy and Performance in
General-Purpose Processor Architectures, R. Balasubramonian,
D.H. Albonesi, A. Buyuktosunoglu, and S. Dwarkadas, U.S. Patent
6,834,328, issued December 21, 2004.
Dynamically Reconfigurable Memory Hierarchy, R. Balasubramonian,
D.H. Albonesi, A. Buyuktosunoglu, and S. Dwarkadas, U.S. Patent
6,684,298, issued January 27, 2004.
Mechanism for Dynamically Adapting the Complexity of a Microprocessor,
D.H. Albonesi, U.S. Patent 6,205,537, issued March 20, 2001.
Electric Cable Connection Error-Detect Method and Apparatus,''
D.H. Albonesi, U.S. Patent 5,170,113, issued December 8, 1992.
Memory Board Selection Method and Apparatus, D.H. Albonesi,
U.S. Patent 5,119,486, issued June 2, 1992.
System Bus for Multiprocessor Computer System, D.H. Albonesi,
B.K. Langendorf, J. Chang, J.G. Faase, and M.J. Homberg, U.S. Patent
5,113,514, issued May 12, 1992.
Memory Error Correction System, D.H. Albonesi, U.S. Patent 4,920,539,
issued April 24, 1990.