The Computer Systems Laboratory H.C. Torng Seminar Series

Securing FPGA-Accelerated Cloud Infrastructures

Jakub Szefer
Yale University

Wednesday, March 3, noon
Virtual Event, via Zoom

Cloud FPGAs give users’ ability to request FPGA resources quickly, flexibly, and on-demand. However, as public cloud providers make FPGAs available to many, potentially mutually-untrusting users, security of these Cloud FPGA deployments needs to be analyzed, and defenses developed. This talk will discuss Cloud FPGA security from the perspective of side and covert channel attacks. Especially we want to address and prevent means for sensitive information, such as cryptographic keys or information about machine learning models from being leaked out. The talk will cover our recent work on thermal channels that can be used to create covert channels between users renting same FPGA over time and voltage-based channels can be used to leak sensitive information across FPGAs (in single-tenant or multi-tenant settings), or can be combined with other existing attacks to perform cross-talk leakage inside the FPGAs (in multi-tenant settings). The talk will also present recent work on extracting input and other information from machine learning models running on remote FPGAs. The talk will end with an overview of some defenses and open challenges in securing Cloud FPGAs.

Jakub Szefer’s research focuses on computer architecture and hardware security. His research encompasses secure processor architectures, cloud security, FPGA attacks and defenses, and hardware FPGA implementation of cryptographic algorithms. His research is supported through National Science Foundation and industry grants and donations. He is currently an Associate Professor of Electrical Engineering at Yale University, where he leads the Computer Architecture and Security Laboratory (CASLAB). Prior to joining Yale, he received Ph.D. and M.A. degrees in Electrical Engineering from Princeton University, and B.S. degree with highest honors in Electrical and Computer Engineering from University of Illinois at Urbana-Champaign. He has received the NSF CAREER award in 2017. Jakub is the author of the first book focusing on processor architecture security: “Principles of Secure Processor Architecture Design”, published in 2018. Recently, he has been promoted to the IEEE Senior Member rank in 2019.

Cornell University, School of Electrical and Computer Engineering and CSL H.C. Torng Seminar Series

Open to all students, faculty, and staff

H.C. Torng Seminar Series: Securing FPGA-Accelerated Cloud Infrastructures