Prof. Christoph Studer┬áhas been awarded NSF CAREER Award “Hardware Accelerated Bayesian Inference via Approximate Message Passing: A Bottom-Up Approach.”

Bayesian inference is a powerful method for extracting statistical information from noisy or corrupted measurements. A growing number of applications relies on real-time (time-critical) Bayesian inference, mainly in the fields of wireless communications and imaging. While the most sophisticated algorithms have been designed for time-insensitive tasks, real-time applications typically rely on simplistic methods that prevent the use of accurate system and signal models. This disparity between theory and practice is mainly caused by the fast progress on the theory and algorithm side and the limited theoretical expertise of most hardware designers. The proposed research aims to bridge the ever-growing gap between theory and practice using a holistic approach that spans the circuit design, algorithm, and theory levels. In addition to improving the efficiency and quality of Bayesian inference in real-time applications, the project will advance future wireless systems through collaboration with the telecommunications industry, along with the development of new tools that are accessible to experts on all levels. The interdisciplinary nature of this project is also the unifying theme across the educational outreach activities. The PI will lead hands-on design sessions for underrepresented minority high-school students and will supervise undergraduates from South America with the goal of increasing participation in interdisciplinary research.

The project builds upon approximate message passing (AMP), a powerful statistical framework that facilitates the design of efficient algorithms and is equipped with analytical tools for characterizing inference complexity and quality. Unfortunately, the theory behind AMP makes it inaccessible to most circuit designers; similarly, the constraints of digital circuit design are generally unknown to algorithm designers and theorists. This project resolves the dichotomy by pursuing a bottom-up research approach in which hardware limitations drive efforts on the algorithm and theory levels. This unconventional research paradigm requires a joint consideration of the major challenges on all levels. In particular, the project evaluates hardware approximations that are key for digital circuit designs, investigates algorithm transforms that enable more efficient architectures, and analyzes the impacts of the proposed circuit-level and algorithm-level optimizations on the inference complexity and quality.

Studer receives NSF CAREER Award