I am an associate professor of electrical and computer engineering and a graduate field member of computer science at Cornell University. My research group is part of the Computer Systems Laboratory, and we broadly work on energy-efficient parallel computer architecture for both high-performance and embedded applications. I am also interested in parallel programming methodologies, hardware specialization, interconnection networks, VLSI chip-design methodologies, and the intersection between computer architecture and future emerging technologies. Building prototype systems is an integral part of my research, as this is one of the best ways to validate assumptions, gain intuition about physical design issues, and provide platforms for future software research.
My research has been recognized with several awards including a Cornell Engineering Research Excellence Award (2015), an AFOSR Young Investigator Program award (2015), an Intel Early Career Faculty Honor Program award (2013), an NSF CAREER award (2012), a DARPA Young Faculty Award (2012), and an IEEE Micro Top Picks selection (2004). My teaching has been recognized with the Ruth and Joel Spira Award for Excellence in Teaching (2016), a Michael Tien '72 Excellence in Teaching Award (2013) and a James M. and Marsha D. McCormick Award for Outstanding Advising of First-Year Engineering Students (2013).
Prior to joining Cornell University, I received my Ph.D. in electrical engineering and computer science from the Massachusetts Institute of Technology. From 2007 to 2009, I was a visiting scholar in the Parallel Computing Laboratory at the University of California at Berkeley; I received an M.Phil. in engineering as a Churchill Scholar at the University of Cambridge in 2000, and received a B.S. in electrical engineering as a Jefferson Scholar at the University of Virginia in 1999.
- Jun 2017: Invited to be a visiting fellow at Clare Hall College and a visiting scholar at the Computer Laboratory at the University of Cambridge, UK during Spring/Summer of 2018
- May 2017: Presentation on our Celerity system-on-chip (in collaboration with UCSD and University of Michigan) was accepted to the 29th ACM/IEEE Symp. on High-Performance Chips (HOTCHIPS'17)
- May 2017: Ian Thompson, Mohammad Dohadwala, James Talmage, and Baturay Turkmen successfully completed their MEng design projects and graduated. Ian is heading to Green Hills Software, Mohammad is heading to Hyperloop, James is heading to Cavium, and Turkmen is heading to Intel – Congratulations!
- May 2017: Taped out the Celerity system-on-chip: a 5x5mm 350M-transistor chip in TSMC 16nm designed and implemented by a large team of over 20 students and faculty from UC San Diego, University of Michigan, and Cornell as part of the DARPA Circuit Realization At Faster Timescales (CRAFT) program. The chip includes a fully synthesizable PLL, digital LDO, five modified Chisel-generated RISC-V Rocket cores, a 496-core RISC-V tiled manycore processor, tightly integrated Rocket-to-manycore communication channels, complex HLS-generated BNN (binarized neural network) accelerator, manycore-to-BNN high-speed links, sleep-mode 10-core manycore, top-level bus interconnect, high-speed source-synchronous off-chip I/O, and a custom flip-chip package. Cornell led the Rocket+BNN accelerator logical/physical physical design and also made key contributions to the top-level logical/physical integration and design/verification methodology.
- May 2017: Gave guest lecture in ENGRI 1210 The Computing Technology Inside Your Smartphone on Recent Trends and Applications in Computer Engineering
- May 2017: Research group celebrated with our end-of-the-semester barbecue
- Mar 2017: Research group moved to the new home of the Computer Systems Laboratory in 471 Rhodes Hall. The space was designed by LEVENBETTS, a leading architecture firm from NYC, to facilitate a sense of community, encourage collaboration, support healthy living, and balance the multi-dimensional aspect of academia. The space includes new PhD offices, lounge space, breakout rooms, and a state-of-the-art hardware prototyping research lab.
- Jan 2017: Ji Kim wins the ECE Outstanding PhD Thesis Award for his thesis titled "Software/Hardware Co-Design to Improve Productivity, Portability, and Performance of Loop-Task Parallel Applications" – Congratulations!
- Jan 2017: Course website for ECE 5745 Complex Digital ASIC Design now online
- Nov 2016: Paper on dynamic hazard resolution for pipelining irregular loops in high-level synthesis (in collaboration with Prof. Zhiru Zhang and his students) was accepted to the 25th ACM ACM Int'l Symp. on Field Symposium on Field-Programmable Gate Arrays (FPGA'17)
- Nov 2016: Invited to serve on the program committees for the IEEE Micro Top Picks special issue, the 44th ACM/IEEE Int'l Symp. on Computer Architecture (ISCA'17), and the ACM/IEEE Conf. on High-Perf Comp, Networking, Storage, and Analysis (SC'17)
- Nov 2016: Gave guest lecture in ECE 3400 Electrical and Computer Engineering Practice and Design on Design Principles and Methodologies in Computer Architecture
- Nov 2016: Promoted to the rank of Associate Professor with indefinite tenure by the Cornell University Board of Trustees
- Sep 2016: Attended the inaugural ARM Research Summit in Cambridge, UK
- Sep 2016: Sarah Mount from The University of Wolverhampton presents her work on extending our Pydgin framework to build a fast instruction set simulator for the Adapteva Epiphany instruction set at PyCon UK 2016 in Cardiff, UK
- Aug 2016: Ji Kim successfully defended his doctoral thesis titled "Software/Hardware Co-Design to Improve Productivity, Portability, and Performance of Loop-Task Parallel Applications". Ji is heading to Google – Congratulations!
- Aug 2016: Course website for ECE 4750 Computer Architecture now online
- Aug 2016: Christopher Torng presented a student poster on our experiences using a novel Python-based hardware modeling framework for computer architecture test chips at the 28th ACM/IEEE Symp. on High-Performance Chips (HOTCHIPS'16)
- All News
Current Research Projects
- Programmable Accelerator-Based Architectures
- General-Purpose Graphics Processing Unit Microarchitecture
- Algorithm and Data-Structure Hardware Specialization
- Architecture and Circuit Co-Design for Integrated Voltage Regulation
- Python-Based Frameworks to Enable a Vertically Integrated Research Methodology
- FPGA/ASIC Prototyping
Educational Outreach Activities
- Curie Academy 2014: Week-Long Design Experience
- ENGRG 1060 Explorations in Engineering: Computer Engineering Unit
- Shreesha Srinath (MS/PhD)
- Christopher Torng (MS/PhD)
- Berkin Ilbeyi (MS/PhD)
- Moyang Wang (MS/PhD)
- Shunning Jiang (MS/PhD)
- Khalid Al-Hawaj (MS/PhD)
- Former Students
- National Science Foundation
- Defense Advanced Research Projects Agency
- Air Force Office of Scientific Research
- Intel Corporation (research funding and equipment donation)
- NVIDIA (research funding and equipment donation)
- Semiconductor Research Corporation (undergraduate research funding)
- Advanced Micro Devices (undergraduate research funding)
- Synopsys (CAD tool donation)
- Xilinx (CAD tool donation)
- ARM (Physical IP donation)
- Conference PC Member: ASPLOS'11, PPoPP'13, ISCA'13/'15/'17, MICRO'15
- Conference PC Member: HPCA'16, SC'16, IEEE Micro TopPicks'16, ISCA'17, SC'17
- Conference External Reviewer: ISCA, ASPLOS, MICRO, HPCA, DAC, SIGMETRICS
- Conference Organizing Committee Member: HPCA'14
- Workshop PC Member: GPGPU'14, WDDD'15, NOPE'15, GPGPU'16, WDDD'16
- Workshop Co-Organizer: WINDS'10, WARP'15
- Tutorial Co-Organizer: PyMTL/Pydgin'15
- Journal Reviewer: JETCAS, TCAD, TVLSI, TACO, CAL, MICPRO, COMPUTER
- Book Reviewer: Morgan and Claypool Synthesis Lectures on Computer Architecture
- Member: IEEE Computer Society, ACM SIGARCH