Predictable Accelerator Design with Time-Sensitive Affine Types. Rachit Nigam, Sachille Atapattu, Samuel Thomas, Theodore Bauer, Apurva Koti, Zhijing Li, Yuwei Ye, Adrian Sampson, Zhiru Zhang. In PLDI:Programming Language Design and Implementation 2020, London, United Kingdom. paper
High performance hardware architectures for Intra Block Copy and Palette Coding for HEVC screen content coding extension. R. Senanayake, Namitha Liyanage, S. Wijeratne, Sachille Atapattu, K. Athukorala, P. M. K. Tharaka, G. Karunaratne, R. M. A. U. Senarath, Ishantha Perera, A. Ekanayake and Ajith Pasqual. In ASAP:IEEE 28th International Conference on Application-specific Systems, Architectures and Processors, Seattle, WA, United States. paper
Real Time All Intra HEVC HD Encoder on FPGA. Sachille Atapattu, Namitha Liyanage, Nisal Menuka, Ishantha Perera and Ajith Pasqual. In ASAP:IEEE 27th International Conference on Application-specific Systems, Architectures and Processors, London, United Kingdom. paper