office: 471E Rhodes Hall, Ithaca, NY 14853
email: mw828 at cornell edu
I am a final-year Ph.D. candidate in Electrical and Computer engineering advised by Professor Christopher Batten at Cornell University. I am pursuing research in the area of parallel computer architectures and programming frameworks. I am particularly interested in developing scalable, energy-efficient, and easy-to-program manycore architectures.
There is a fundamental trade-off between hardware scalability and software programmability in manycore architectures. Manycore processors with heterogeneous cache coherence (a combination of hardware- and software-based cache coherence) can offer tremendous peak throughput while being complexity and energy efficient. Unfortunately, programming these heterogeneous cache-coherent systems to enable collaborative execution is challenging, especially when considering dynamic task parallelism. My recent work [ISCA'20] seeks to address this challenge using a combination of light-weight software and hardware techniques. It provides a familiar TBB/Cilk-like task-based parallel programming model on heterogeneous cache-coherent systems. It also enables efficient collaborative execution on dynamic task-parallel applications.
In the past, I have developed an asymmetry-aware work-stealing runtime to improve the performance and energy efficiency of multicore processors [ISCA'16]. I have also contributed to the runtime for programmable accelerators [MICRO'17].
manycore architectures, parallel programming frameworks, programmable accelerators
- Moyang Wang, Tuan Ta, Lin Cheng, and Christopher Batten. "Efficiently Supporting Dynamic Task Parallelism on Heterogeneous Cache-Coherent Systems." ACM/IEEE Int’l Symp. on Computer Architecture (ISCA-47), June 2020. [pdf, slides, video]
- Ji Kim, Shunning Jiang, Christopher Torng, Moyang Wang, Shreesha Srinath, Berkin Ilbeyi, Khalid Al-Hawaj, and Christopher Batten. Using Intra-Core Loop-Task Accelerators to Improve the Productivity and Performance of Task-Based Parallel Program. 50th ACM/IEEE Int'l Symp. on Microarchitecture (MICRO-50), October 2017. [link, pdf, slides, poster]
- Christopher Torng, Moyang Wang, Bharath Sudheendra, Nagaraj Murali, Suren Jayasuriya, Shreesha Srinath, Taylor Pritchard, Robin Ying, and Christopher Batten. "Experiences Using A Novel Python-Based Hardware Modeling Framework For Computer Architecture Test Chips". Poster at the 28th Symposium on High Performance Chips (HotChips-28), August 2016. [pdf, slides, poster]
- Christopher Torng, Moyang Wang, and Christopher Batten. "Asymmetry-Aware Work-Stealing Runtimes". 43rd ACM/IEEE Int'l Symp. on Computer Architecture (ISCA-43), June 2016. [link pdf, slides, errata]
- BRGTC1 test chip tapeout (2016) -- BRGTC1 (image) is the BRG research group's first computer architecture test chip. It is a 2x2mm 1.3M-transistor chip in IBM 130nm designed and implemented using our new PyMTL hardware modeling framework. The chip includes a simple pipelined 32-bit RISC processor, custom LVDS clock receiver, 16KB of on-chip SRAM, and application-specific accelerators generated using commercial C-to-RTL high-level synthesis tools. This project was co-lead by Christopher Torng. Other students who worked on this project: Bharath Sudheendra and Nagaraj Murali (physical design), Suren Jayasuriya and Robin Ying (full-custom design), Shreesha Srinath (accelerator design), Mark Buckler (toolflow), and Taylor Pritchard (FPGA emulation).
- Lead Graduate TA - ECE 4750 / CS 4420 Computer Architecture - Fall 2015
- Facebook - Software Engineer, PhD Intern - Menlo Park, CA, USA - Summer 2018
- Cornell H.C. Torng Fellowship 2014