Title: Internet of Things: Information Analytics, Energy-Efficiency and Hardware Security
Date/time: Monday, Oct. 31 @ 4:15pm
Location: 233 Phillips Hall
Host: Prof. Christoph Studer
Abstract: This talk will address VLSI architectures for emerging internet-of-things. Machine learning and information analytics are important components in all these things. Reducing energy consumption and silicon area are also critical for these things. Enhancing security and preventing piracy are also of critical concern. Almost all things should have embedded classifiers to make decisions on data. Thus, reducing energy consumption of features and classifiers is important.
First part of the talk will present energy reduction approaches for a medical internet-of-thing for monitoring EEG and predicting seizures. In the second part of the talk, I will addresses hardware security and present approaches to designing circuits that cannot be easily reverse engineered and cannot be pirated. To this end, authentication and obfuscation approaches will be presented. In the third part of the talk, I will describe approaches to molecular and DNA computing. In particular, I will describe the unknown synergies between stochastic logic and molecular computing, and how stochastic logic implementations can be translated into DNA computing systems.
Bio: Keshab K. Parhi received the B.Tech. degree from the Indian Institute of Technology (IIT), Kharagpur, in 1982, the M.S.E.E. degree from the University of Pennsylvania, Philadelphia, in 1984, and the Ph.D. degree from the University of California, Berkeley, in 1988. He has been with the University of Minnesota, Minneapolis, since 1988, where he is currently Distinguished McKnight University Professor and Edgar F. Johnson Professor in the Department of Electrical and Computer Engineering. He has published 595 papers, is the inventor of 29 patents, and has authored the textbook VLSI Digital Signal Processing Systems (Wiley, 1999) and coedited the reference book Digital Signal Processing for Multimedia Systems (Marcel Dekker,
1999).
Dr. Parhi is widely recognized for his work on high-level transformations of iterative data-flow computations, for developing a formal theory of computing for design of digital signal processing systems, and for his contributions to multi-gigabit Ethernet systems on copper and fiber and for backplanes. His current research addresses VLSI architecture design of signal processing, communications and biomedical systems, error control coders and cryptography architectures, high- speed transceivers, stochastic computing, hardware security, and molecular computing. He is also currently working on intelligent classification of biomedical signals and images, for applications such as seizure prediction and detection, schizophrenia classification, biomarkers for mental disorders, brain connectivity, and diabetic retinopathy screening.
Dr. Parhi is the recipient of numerous awards including the 2012 Charles A. Desoer Technical Achievement award from the IEEE Circuits and Systems Society, the 2004 F. E. Terman award from the American Society of Engineering Education, the 2003 IEEE Kiyo Tomiyasu Technical Field Award, the 2001 IEEE W. R. G. Baker prize paper award, and a Golden Jubilee medal from the IEEE Circuits and Systems Society in 2000. He was elected a Fellow of IEEE in 1996. He served as the Editor-in-Chief of the IEEE Trans. Circuits and Systems, Part I during 2004-2005 and as an elected member of the Board of Governors of the IEEE Circuits and Systems society from 2005 to 2007.