Technology scaling will soon enable high-performance processors with hundreds of cores integrated onto a single die, but the success of such systems could be limited by the corresponding chip-level interconnection networks. Nanophotonic networks are a promising direction that attempt to provide improved performance, bandwidth density, and energy efficiency compared to projected electrical networks. There has recently been significant progress at the nanophotonic device level, and there have also been many recent system-level proposals that explore how to use these devices in intra- and inter-chip networks. The goal of this workshop was to bring together device-level and system-level nanophotonic researchers to talk about their work and to share their experiences with this emerging technology.

This full-day workshop was held on Sunday, December 5, 2010, co-located with MICRO-43 in Atlanta, GA. Over thirty researchers participated in the workshop, which included two short tutorial presentations, several invited speakers, and a diverse set of eight presentations selected by the technical program committee based on extended abstract submissions. Abstracts and slides from many of the talks are included below.

Program

8:00	–	8:45	am	Breakfast
8:45	–	9:00	am	Welcoming Remarks	slides
9:00	–	9:30	am	Invited Tutorial: Microphotonics for Next Generation Computers Michael Watts (MIT)	abstract
9:30	–	10:00	am	Invited Tutorial: Designing Nanophotonic Interconnection Networks Christopher Batten (Cornell University)	abstract slides
10:00	–	10:30	am	Morning Break
10:30	–	10:50	am	Invited Talk: Future State-of-the-Art Electrical Interconnect Byungsub Kim (Intel)	abstract slides
10:50	–	11:10	am	Invited Talk: Scaling and Designing Nanomodulators for Chip-Level Integration Sasikanth Manipatruni (GE Global Research)	abstract slides
11:10	–	12:00	pm	Keynote: The Oracle Macrochip: Architecture and Devices Frankie Liu and Michael O. McCracken (Oracle, Sun Labs)	abstract
12:00	–	1:30	pm	Lunch
1:30	–	1:50	pm	EOS: A Monolithic CMOS Photonic Platform V. Stojanović, R. Ram, M. Popović, J. Orcutt, M. Georgas, J. Leu, B. Moss, C. Sun, J. Sun, H. Li (MIT)
1:50	–	2:10	pm	Scalable Nanophotonic Interconnect for Cache-Coherent Multicores R.W. Morris and A.K. Kodi (Ohio University)	abstract slides
2:10	–	2:30	pm	Device Guidelines for WDM Interconnects Using Silicon Microring Resonators N. Sherwood-Droz, K. Preston, J.S. Levy, M. Lipson (Cornell University)	abstract
2:30	–	2:50	pm	An Investigation into System-Level Trimming Issues in On-Chip Nanophotonic Networks C. Nitta, M. Farrens, V. Akella (U.C. Davis)	abstract slides
2:50	–	3:30	pm	Afternoon Break
3:30	–	3:50	pm	Initial Results of Prototyping a 3D Integrated Intra-Chip Free-Space Optical Interconnect B. Ciftcioglu, R. Berman, J. Zhang, Z. Darling, A. Garg, J. Hu, M. Jain, P. Liu, I. Savidis, S. Wang, J. Xue, E. Friedman, M. Huang, D. Moore, G. Wicks, H. Wu (University of Rochester)	abstract slides
3:50	–	4:10	pm	Towards Chip-Scale Plasmonic Interconnects H.M.G. Wassel, M. Tiwari1, J.K. Valamehr, L. Theogarajan, J. Dionne, F.T. Chong, and T. Sherwood (U.C. Santa Barbara & Stanford)	abstract slides
4:10	–	4:30	pm	Exploring Benefits and Designs of Optically Connected Disintegrated Processor Architecture Y. Pan, Y. Demir, N. Hardavellas, J. Kim, G. Memik (Northwestern University & KAIST)	abstract slides
4:30	–	4:50	pm	Implementing System-in-Package with Nanophotonic Interconnect M. Cianchetti, N. Sherwood-Droz, C. Batten (Cornell University)	abstract slides

Committee

• Workshop Organizer
• Christopher Batten (Cornell University)
• Program Committee Chairs
• David Albonesi (Cornell University)
• José F. Martínez (Cornell University)
• Program Committee
• Nathan Binkert (HP Labs)
• Luca Carloni (Columbia University)
• Ajay Joshi (Boston University)
• Nevin Kırman (Intel Labs)
• Herb Schwetman (Oracle, Sun Labs)

Flyers

• [ txt, pdf ] Call for Papers
• [ txt, pdf ] Call for Participation