The purpose of this tutorial was to introduce the computer architecture community to the features and capabilities of two new Python-based frameworks: PyMTL (published in MICRO'14) and Pydgin (published in ISPASS'15). This half-day tutorial was held on Sunday, June 14, 2015, co-located with ISCA-42 in Portland, OR. Over thirty researchers participated in the workshop, which included a mix of presentations and hands-on activities.

PyMTL is a hardware modeling framework for vertically integrated computer architecture research. The PyMTL framework encourages a philosophy of "modeling towards layout" in which a microarchitecture is incrementally refined from a high-level functional-level model, to a timing-approximate cycle-level model, to a bit-accurate RTL implementation. PyMTL is particularly well-suited for rapid design space exploration of microarchitectures for novel accelerators, specialized coprocessors, or any design proposal that could benefit from the additional credibility provided by an RTL implementation.

Pydgin is a framework for rapidly developing instruction-set simulators (ISSs) from a Python-based architecture description language. Pydgin creatively adapts existing meta-tracing JIT compilation frameworks designed for general-purpose dynamic programming languages to automatically generate ISSs augmented with dynamic binary translation. Pydgin is suitable for generating very fast ISSs for general-purpose instruction sets, but is particularly well-suited for exploring the hardware/software abstraction of emerging specialized architectures.

Our objective was to provide attendees with answers to the following questions:

Tutorial Schedule

8:308:50am Virtual Machine Installation and Setup
While attendees are welcome to simply listen during the tutorial, we strongly encourage attendees to engage in the hands-on activities throughout the tutorial. Attendees should arrive at 8:30am so that there is time to install and setup the virtual machine for the hands-on activities.
8:509:00am Presentation: PyMTL/Pydgin Tutorial Overview slides
9:009:10am Presentation: Introduction to Pydgin slides
9:1010:00am Hands-On: Adding a GCD Instruction using Pydgin
We will first experiment with Euclid's greatest common divisor (GCD) algorithm using the Python interpreter, before adding a new GCD instruction to Pydgin. We will extend the PARC instruction-set simulator (ISS) with the new instruction's encoding and semantics and use small assembly tests to verify these changes. We will instrument the ISS to track a new statistic, use inline assembly to write a microbenchmark, and then roughly compare the performance with and without the new instruction. Finally, we will compare the ISS performance using the Python interpreter vs. the high-performance C-based simulator automatically generated by Pydgin.
10:0010:10am Presentation: Introduction to PyMTL slides
10:1011:00am Hands-On: PyMTL Basics with a RegIncr
We will first build a simple registered incrementer model to understand basic PyMTL syntax, constructs, and semantics including PyMTL's emphasis on concurrent structural modeling. We will learn how to simulate our model of a registered incrementer and how to write unit tests using the popular py.test framework. We will translate this model into Verilog, and then use the same unit tests to verify the translated Verilog. We will also experiment with PyMTL's powerful structural composition and parameterized elaboration features.
11:0011:30am Coffee Break
11:3011:40am Presentation: Multi-Level Modeling with PyMTL slides
11:4012:30pm Hands-On: FL, CL, RTL Modeling of a GCD Unit
Using what we have learned before the coffee break, we will incrementally build, test, and evaluate a simple GCD unit as an example of a new "in-core" accelerator. We will study functional-level (FL), cycle-level (CL), and register-transfer-level (RTL) models of the GCD unit. We will see how to use BitStructs, port bundles, latency insensitive interfaces, and interface adapters to simplify multi-level modeling. We will experiment with latency insensitive test harnesses that are reusable across FL, CL, and RTL models. We will augment our CL model with cycle-approximate timing, and will fix a bug in our RTL model.
12:301:30pm Lunch

Tutorial Prerequisites

We expect attendees that wish to engage in the hands-on activities throughout the tutorial to have some experience with Linux-based software and/or hardware development (e.g., working at the Linux command line, using a Linux text editor such as emacs, vim, or gedit). Attendees should bring a laptop and charger for the tutorial. Each attendee will receive a USB flash drive containing: VirtualBox installers for Windows, Mac OS X, Linux; a CentOS-based virtual machine containing all of the code and tools for the tutorial; and PDFs for all of the tutorial slides and handouts. While it is certainly possible to install the PyMTL and Pydgin frameworks on your own UNIX-like laptops, we encourage attendees to use our virtual machine to simplify the setup. Attendees will need approximately 10GB of free space in order to install and use the VirtualBox virtual machine.

Tutorial Organizers

PyMTL and Pydgin Publications

PyMTL and Pydgin GitHub Repositories

Please note that both projects are still under active development and subject to change.