Title: Automatically Finding and Fixing Cache Contention Bugs
Speaker:
Joe Devietti, University of Princeton
Date/Time:
Wednesday, November 30th @ 12:15pm
Location:
310 Rhodes Hall
Host:
Adrian Sampson

Abstract: Multicore architectures continue to pervade every part of our computing infrastructure, from servers to phones and smart watches. While these parallel architectures bring established performance and energy-efficiency gains compared to single-core designs, parallel code written for these architectures can suffer from subtle performance bugs that are difficult to understand and repair with current tools.

We’ll discuss two systems that leverage hardware-software co-design to tackle cache contention bugs like false sharing, in the context of both unmanaged languages like C/C++ and managed languages like Java. These systems use hardware performance counters for efficient bug detection, and novel runtime systems to repair bugs online without any programmer intervention. Along the way, we’ll discuss some subtle memory consistency model issues brought to light by these optimizations.

Bio: Joseph Devietti is an Assistant Professor in the Department of Computer & Information Science at the University of Pennsylvania. His research focuses on making multicore computers easier to program, leveraging techniques across the computing stack, including computer architecture, compilers, runtime systems and programming languages. He was awarded an Intel Early Career Faculty Honor in 2013. He earned his PhD in Computer Science & Engineering from the University of Washington in 2012.

CSL Seminar: Joe Devietti, University of Princeton