David H. Albonesi
Professor David Albonesi joined the Computer Systems Laboratory in 2004 after serving on the faculty of the University of Rochester. His current research interests include adaptive and reconfigurable multi-core and processor architectures, power- and reliability-aware computing, and energy-efficient smart buildings. In addition to his academic experience, he has ten years of industry experience as a technical manager, computer architect, and chip designer at IBM and Prime Computer.
Dr. Albonesi is a Fellow of the IEEE, and has received the National Science Foundation CAREER Award, three IBM Faculty Awards, three IEEE Micro Top Picks paper awards, and the Michael Tien '72, Ralph S. Watts '72, and Ruth and Joel Spira Excellence in Teaching Awards. He serves on the Editorial Board of IEEE Computer, and was Editor-in-Chief of IEEE Micro from 2007-10. Professor Albonesi was General co-Chair of the 42nd International Symposium on Microarchitecture and Program Chair of the 42nd International Symposium on Computer Architecture. He is a graduate field member of ECE and CS, and teaches courses ranging from freshman-level introductory computing to advanced graduate topics in computer systems.
DeepRecon: Dynamically Reconfigurable Architecture for Accelerating Deep Neural Networks, T. Rzayev, S. Moradi, D.H. Albonesi, and R. Manohar, International Joint Conference on Neural Networks, May 2017.
Toolbox for Exploration of Energy-Efficient Event Processors for Human-Computer Interaction, T. Rzayev, D.H. Albonesi, R. Manohar, F. Guimbretiere, and J. Kihm, International Symposium on Performance Analysis of Systems and Software, April 2017.
Dynamic GPGPU Power Management Using Adaptive Model Predictive Control, A. Majumdar, L. Piga, I. Paul, J.L. Greathouse, W. Huang, and D.H. Albonesi, 23rd International Symposium on High Performance Computer Architecture, February 2017.
Fractured Arithmetic Accelerator for Training Deep Neural Networks, T. Rzayev, S. Moradi, D.H. Albonesi, and R. Manohar, Workshop on Hardware and Algorithms for On-chip Learning, held at the International Conference on Computer-Aided Design, November 2016.
Characterizing the Benefits and Limitations of Smart Building Meeting Room Scheduling, A. Majumdar, Z. Zhang, and D.H. Albonesi, 7th International Conference on Cyber-Physical Systems, April 2016.
Energy-Comfort Optimization using Discomfort History and Probabilistic Occupancy Prediction, A. Majumdar, J.L. Setter, J.R. Dobbs, B.M. Hencey, and D.H. Albonesi, 5th International Green Computing Conference, November 2014.
Flicker: A Dynamically Adaptive Architecture for Power Limited Multicore Systems, P. Petrica, A.M. Izraelevitz, D.H. Albonesi, and C.A. Shoemaker, 40th International Symposium on Computer Architecture, June 2013.