David H. Albonesi
Professor
Computer Systems Laboratory
School of Electrical and Computer Engineering
Cornell University
333 Rhodes Hall
Ithaca, NY 14853
(607) 254-5473
albonesi at csl.cornell.edu
Professor David Albonesi joined the Computer Systems Laboratory in 2004 after serving on the faculty of the University of Rochester. His current research interests include adaptive and reconfigurable multi-core and processor architectures, power- and reliability-aware computing, and high performance interconnect architectures using silicon nanophotonics. In addition to his academic experience, he has ten years of industry experience as a technical manager, computer architect, and chip designer at IBM and Prime Computer.
Dr. Albonesi is a Fellow of the IEEE, and has received the National Science Foundation CAREER Award, three IBM Faculty Awards, three IEEE Micro Top Picks paper awards, and the Michael Tien '72 Excellence in Teaching Award. He serves on the Editorial Board of ACM Transactions on Architecture and Code Optimization, was Editor-in-Chief of IEEE Micro from 2007-10, and General co-Chair of the 42nd International Symposium on Microarchitecture. He is a graduate field member of ECE and CS, and teaches courses ranging from freshman-level introductory computing to advanced graduate topics in computer systems.
Selected recent publications
A Low Latency, High Throughput On-Chip Optical Router Architecture for Future Chip Multiprocessors, M.J. Cianchetti and D.H. Albonesi, ACM Journal on Emerging Technologies in Computing Systems, Special Issue on Nanophotonic Communication Technology Integration, Vol. 7, Issue 2, June 2011.
ReMAP: A Reconfigurable Architecture for Chip Multiprocessors, M.A. Watkins and D.H. Albonesi, IEEE Micro, Special Issue on the Top Picks from the Computer Architecture Conferences, January/February 2011.
Scalable Thread Scheduling and Global Power Management for Heterogeneous Many-Core Architectures, J.A. Winter, D.H. Albonesi, and C.A. Shoemaker, 19th International Conference on Parallel Architectures and Compilation Techniques, pp. 29-39, September 2010.
Dynamically Managed Multithreaded Reconfigurable Architectures for Chip Multiprocessors, M.A. Watkins and D.H. Albonesi, 19th International Conference on Parallel Architectures and Compilation Techniques, pp. 41-52, September 2010.
Dynamic Power Redistribution in Failure Prone CMPs, P. Petrica, J.A. Winter, and D.H. Albonesi, Workshop on Energy Efficient Design, held at the 37th International Symposium on Computer Architecture, June 2010.