David H. Albonesi
Computer Systems Laboratory
Professor David Albonesi joined the Computer Systems Laboratory in 2004 after serving on the faculty of the University of Rochester. His current research interests include adaptive and reconfigurable multi-core and processor architectures, power- and reliability-aware computing, and energy-efficient smart buildings. In addition to his academic experience, he has ten years of industry experience as a technical manager, computer architect, and chip designer at IBM and Prime Computer.
Dr. Albonesi is a Fellow of the IEEE, and has received the National Science Foundation CAREER Award, three IBM Faculty Awards, three IEEE Micro Top Picks paper awards, and the Michael Tien '72 Excellence in Teaching Award. He serves on the Editorial Boards of ACM Transactions on Architecture and Code Optimization and IEEE Computer, was Editor-in-Chief of IEEE Micro from 2007-10, and General co-Chair of the 42nd International Symposium on Microarchitecture. He is a graduate field member of ECE and CS, and teaches courses ranging from freshman-level introductory computing to advanced graduate topics in computer systems.
Flicker: A Dynamically Adaptive Architecture for Power Limited Multicore Systems, P. Petrica, A.M. Izraelevitz, D.H. Albonesi, and C.A. Shoemaker, 40th International Symposium on Computer Architecture, June 2013.
Energy-Aware Meeting Scheduling Algorithms for Smart Buildings, A. Majumdar, D.H. Albonesi, and P. Bose, 4th ACM Workshop on Embedded Systems for Energy-Efficiency in Buildings, November 2012.
A Phase Adaptive Cache Hierarchy for SMT Processors, S. Lopez, O. Garnica, D.H. Albonesi, S. Dropsho, J. Lanchares, and J.I. Hidalgo, Microprocessors & Microsystems, Vol. 35, No. 8, pp. 683-694, November 2011.
A Low Latency, High Throughput On-Chip Optical Router Architecture for Future Chip Multiprocessors, M.J. Cianchetti and D.H. Albonesi, ACM Journal on Emerging Technologies in Computing Systems, Special Issue on Nanophotonic Communication Technology Integration, Vol. 7, Issue 2, June 2011.
ReMAP: A Reconfigurable Architecture for Chip Multiprocessors, M.A. Watkins and D.H. Albonesi, IEEE Micro, Special Issue on the Top Picks from the Computer Architecture Conferences, January/February 2011.
Scalable Thread Scheduling and Global Power Management for Heterogeneous Many-Core Architectures, J.A. Winter, D.H. Albonesi, and C.A. Shoemaker, 19th International Conference on Parallel Architectures and Compilation Techniques, pp. 29-39, September 2010.