Cornell ECE 5775

ECE 5997 Hardware Accelerator Design and Automation
Fall 2021

Course Texts

Ryan Kastner, Janarbek Matai, and Stephen Neuendorffer, Parallel Programming for FPGAs, arXiv, 2018.
Giovanni De Micheli, Synthesis and Optimization of Digital Circuits, McGraw-Hill, 1994.

Course Schedule

Lectures: Fri 4:40-5:55pm, Rhodes 310
Tutorials: Tue 4:40-5:55pm

Fri 10/15 – Introduction

Slides
Readings

Course Syllabus

Tue 10/19 – HLS Tool Tutorial

Slides
Readings

Kastner, Matai, and Neuendorffer: Ch. 1.1, 1.4, 2.1-2.4

Fri 10/22 – Hardware Specialization

Slides
Readings

Kastner, Matai, and Neuendorffer: Ch. 1.2-1.3
W.J. Dally, Y. Turakhia, and S. Han. Domain-specific hardware accelerators. CACM, Feb. 2020.

Wed 10/27 – Lab 1 Due: CORDIC Design

Assignment
Readings

Kastner, Matai, and Neuendorffer: Ch. 3.1-3.3
Xilinx, Inc. Vivado Design Suite User Guide: High-Level Synthesis. Ch. 4: p391-393, p.524-558
(regarding the usage of Vivado HLS Tcl directives and the ap_fixed class).

Fri 10/29 – Control Data Flow Graph

Slides
Readings

Schaumont: Ch. 4
F. E. Allen. Control Flow Analysis. Symp. on Compiler Optimization. 1970.

Fri 11/05 – Scheduling

Slides
Readings

De Micheli: Ch. 2.3.4, 5.1–5.4.1

Wed 11/10 – Lab 2 Due: Digit Recognition System (Part 1)

Assignment
Readings

J. Kun. K-Nearest-Neighbors and Handwritten Digit Classification. Aug. 2012.
Xilinx, Inc. Vivado Design Suite User Guide: High-Level Synthesis. Ch. 1: p121-145
(regarding the throughput optimization).

Fri 11/12 – More Scheduling

Slides
Readings

De Micheli: 5.4.2 & 5.4.3
J. Cong and Z. Zhang. An Efficient and Versatile Scheduling Algorithm Based on SDC Formulation. Design Automation Conf., 2006.
S. Dai, G. Liu, and Z. Zhang. A Scalable Approach to Exact Resource-Constrained Scheduling Based on a Joint SDC and SAT Formulation. Int'l Symp. on Field-Programmable Gate Arrays, 2018.

Fri 11/19 – Resource Sharing; Pipelining

Slides
Readings

De Micheli: Ch. 4.3, 6.7

Tue 11/23 – Neural Network Tutorial

Slides
Readings

L. Fei-Fei, J. Johnson, and S. Yeung. Stanford CS231n Convolutional Neural Networks for Visual Recognition.

Wed 12/1 – Lab 3 Due

Fri 12/03 – More Pipelining

Slides
Readings

Z. Zhang and B. Liu. SDC-Based Modulo Scheduling for Pipeline Synthesis. Int'l Conf. on Computer-Aided Design, 2013.

Tue 12/07 – DNN Acceleration on FPGAs

Slides
Readings

C. Zhang, P. Li, G. Sun, Y. Guan, B. Xiao, and J. Cong. Optimizing FPGA-Based Accelerator Design for Deep Convolutional Neural Networks. Int'l Symp. on Field-Programmable Gate Arrays, 2015.