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Ji Kim

Ji Kim
Ph.D. Student, ECE

Office: 364 Upson Hall, Ithaca, NY 14853 USA
Email: ji(at)csl(dot)cornell(dot)edu

My research focuses on fine-grain heterogeneous architectures with support for seamless adaptive execution of amorphous data parallel tasks across general-purpose and specialized accelerator cores. While we are reaching the limits of what we can accomplish by simply adding more cores onto a chip, computer architects are turning towards new abstractions to take advantage of the growing transistor density. Although current approaches of coarse-grain heterogeneity are promising, there are significant challenges with unifying the parallelism abstraction, support for programming APIs and compilers, as well as efficient adaptivity. I am interested in exploring potential unifying architectures for exposing, scheduling, and executing fine-grain parallel tasks to improve performance and energy efficiency on applications with varying levels of amorphous data parallelism. Part of this vision is innovating designs of data-parallel accelerators using mechanisms to eliminate redundancy and improve load balancing.

Research Interests

Fine-Grain Heterogeneous Architectures, Energy-Efficient Data-Parallel Accelerators, Amorphous Data Parallelism, Vertically Integrated Design Methodology


Cornell University, Ithaca, NY

  • Doctor of Philosophy (Ph.D.), Electrical & Computer Engineering (Computer Architecture), 2010-Present

University of Pennsylvania, Philadelphia, PA

  • Masters of Science in Engineering (MSE), Electrical Engineering, 2006-2010
  • Bachelor of Science in Engineering (BSE), Electrical Engineering, 2006-2010



  • Ji Kim. Exposing, Scheduling, and Executing Fine-Grain Parallel Tasks. Thesis Proposal, Cornell University, October 2014.
  • Ji Kim. Morph Algorithms on GPGPUs. Paper Presentation for Cornell Systems Lunch, Cornell University, September 2013.
  • Ji Kim. Complexity-Effective Heterogeneous Specialization for Explicit-Loop Architectures. Poster for ECE Visit Day, Cornell University, April 2012.

Previous Research Experience

  • Implementation of Computation Group, Professor Andre DeHon, 2009-2010, University of Pennsylvania
    • Research on lifetime performance modeling of self-correcting FPGAs based on incremental timing-analysis of routing faults.

Professional Experience

Teaching Experience


  • ECE 5715: Computer Hardware Design Practicum
  • ECE 5720: Parallel Computer Architecture
  • ECE 5750: Advanced Computer Architecture
  • ECE 5950: Complex Digital ASIC Design


  • 2012 NDSEG Fellowship
  • 2012 ECE Director's TA Award
    • Awarded to best TA of academic year.
  • 2010 Cornell University Fellowship
    • Selective one-semester graduate fellowship.
  • 2010 Honorable Harold Berger Award
    • For technical innovation and entrepreneurial possibility of senior design project, Voice over IP with Enhanced Resiliency (VIPER).
  • 2010 SEAS Senior Design Competition Honorable Mention
  • Hugo Otto Wolf Memorial Prize
    • Awarded to one senior student in each engineering major.
  • IEEE Student Award
    • For great contribution to the IEEE student branch.
  • President of IEEE student branch at the University of Pennsylvania
  • President of Eta Kappa Nu Lambda Chapter
  • Tau Beta Pi
  • Dean's List 2006-07, 07-08, 08-09, 09-10