Christopher Batten
Professor
Computer Systems Laboratory
School of Electrical and Computer Engineering
College of Engineering
Cornell University
office: 323 Rhodes Hall, Ithaca, NY 14853
phone: (607) 255-2672
email: cbatten cornell edu
I am a Professor of Electrical and Computer Engineering and a graduate field member of Computer Science at Cornell University. My research group is part of the Computer Systems Laboratory, and we largely work at the intersection of computer architecture, electronic design automation, and digital VLSI including projects on parallel programming frameworks, programmable accelerator design, interconnection networks, productive VLSI chip design methodologies, and architectures for future emerging technologies. Building prototype systems is an integral part of my research, as this is one of the best ways to validate assumptions, gain intuition about physical design issues, and provide platforms for future software research.
My research has been recognized with several awards including the ACM/IEEE MICRO Hall of Fame, a Cornell Engineering Research Excellence Award, an AFOSR Young Investigator Program award, an Intel Early Career Faculty Honor Program award, an NSF CAREER award, a DARPA Young Faculty Award, an IEEE Micro Top Picks selection, and MLCAD Best Artifact Award. My teaching has been recognized with the Ruth and Joel Spira Award for Excellence in Teaching, a Kenneth A. Goldman '71 Teaching Award, three Michael Tien '72 Excellence in Teaching Awards, Canaan Family Award for Excellence in Academic Advising, a James M. and Marsha D. McCormick Award for Outstanding Advising of First-Year Engineering Students, and twice as the most influential college educator of a Merrill Presidential Scholar (Courtney Golden BS'23 and Aidan McNay BS'24).
In 2023–2024, I was a Visiting Scholar at the University of California, Berkeley working in the SLICE Lab and a Visiting Professor at NVIDIA working in the Accelerator & VLSI Research Group. In 2018, I was a Visiting Scholar at the Computer Laboratory at the University of Cambridge and a Visiting Fellow at Clare Hall in Cambridge, UK. Prior to joining Cornell University, I received my Ph.D. in Electrical Engineering and Computer Science from the Massachusetts Institute of Technology. I received an M.Phil. in Engineering as a Churchill Scholar at the University of Cambridge in 2000, and received a B.S. in Electrical Engineering as a Jefferson Scholar at the University of Virginia in 1999.
Recent News
- Oct 2026: Received an Duffield Engineering EPICC Award recognizing faculty and staff who exemplify the college’s core values including excellence, purpose, innovation, community, and collaboration
- Oct 2026: Paper on an open-source all-digital source-synchronous inter-chip link silicon validated in TSMC 65nm is accepted to the Asia and South Pacific Design Automation Conference (ASP-DAC) University LSI Design Contest
- Sep 2026: Presented progress on experiential learning for semiconductor chip design through student-led project teams at the NORDTECH Workforce Development Summit in Ithaca, NY
- Sep 2026: Received a third Michael Tien '72 Excellence in Teaching Award (one of the highest award for teaching in the College of Engineering at Cornell University)
- Sep 2026: Presented an update on Cornell's first tape-out class in 20+ years as part of a workshop for the Center for Education of Microchip Designers
- Aug 2026: Course website for ECE 2300 Digital Logic and Computer Organization now online
- Jun 2026: 47 students taped out 20 1x1mm chips on TSMC 180nm through MUSE as part of the completely redesigned version of ECE 6745 Digital ASIC Design. The tape-outs included hardware accelerators for binary neural networks, matrix multiplication, encryption, image processing, approximate multiplication, DNA alignment, vector processing, CORDIC, spiking neural networks, and priority queues. One tape-out also integrated 25 macros implemented using the student's tiny RTL-to-GDS flows. The chips will be assembled in CPGA packages by QP Technologies in August, and the students will test their chips in the lab using a custom designed testing platform this fall. See this poster for more information.
- Jun 2026: C2S2 taped out three 2x2.5mm chips on TSMC 180nm through MUSE: a digital system-on-chip with a RISC-V RV32IM core, matrix-multiplication accelerator, and 16KB of SRAM; an analog chip with an adiabatic flash ADC and asynchronous SAR ADC; and an RFIC chip with a 2.4GHz on-off keying transceiver pipeline.
- Jun 2026: Zhantong Qiu presented our work on a new gem5 model for ARM Cortex-M processors at the gem5 user's workshop held in conjunction with ISCA in Raleigh, NC
- Jun 2026: Created and led a half-day hands-on tutorial on digital chip design for members of the Cornell Tech Policy Institute working on semiconductor supply chain security. The tutorial introduced transistors, CMOS fabrication, digital circuits, and logic gates before guiding participants through the use of commercial EDA tools to create a tapeout-ready 1x1mm chip in TSMC 180nm.
- Jun 2026: Derin Ozturk presented a poster on a new roboarch co-simulation framework for resource-constrained multi-robot teams, at the Workshop on Robotics Acceleration with Computing Hardware (RoboARCH) held in conjunction with ICRA in Vienna, Austria
- May 2026: Parker Schless completed his MEng design project. Parker is graduating and heading to Apple – Congratulations!
- May 2026: Parker Schless's MEng design project titled "Zepplin: A Modular Superscalar Processor" won first place during the annual ECE MEng poster session – Congratulations!
- May 2026: C2S2's end-of-year presentations covered their recent work on three TSMC 180nm tapeouts
- Apr 2026: Kaan Akan received undergraduate research funding from the Duffield Engineering Undergraduate Research Grants Program to explore customized computer architectures for millimeter-scale vision systems
- Feb 2026: Great article about the Cornell Custom Silicon Systems project team in the Cornell Daily Sun
- Jan 2026: Course website for ECE 6745 Complex Digital ASIC Design now online
- Dec 2025: Empire AI proposal for GPU time to explore ultra-long context foundation models for annotated genomic sequences is funded
- All News
Teaching
- ECE 2300 Digital Logic and Computer Organization
- ECE 2400 Computer Systems Programming
- ECE 4750 Computer Architecture
- ECE 6745 Complex Digital ASIC Design
- ECE 5970 Special Topics: Chip-Level Interconnection Networks
Educational Outreach Activities
- CSMore: Week-Long Computer Systems Unit
- Curie Academy 2021: Week-Long Design Experience
- ENGRG 1050 Engineering Seminar: Computer Engineering Hands-On Experience
- ENGRG 1060 Explorations in Engineering: Computer Engineering Unit
- Curie Academy 2014: Week-Long Design Experience
Research Group
- Derin Ozturk (MS/PhD)
- Niklas Schmelzle (MS/PhD)
- Elton Shih (MS/PhD)
- Demetrios Gavalas (MEng)
- Irwin Wang (BS)
- Zephan Sanghani (BS)
- Kaan Akan (BS)
- Kevin Ha (BS)
- Ivan Mokeyev (BS)
- Simeon Turner (BS)
- Former Members
Research Sponsors
- National Science Foundation: CSSI'23, PPoSS'21, SHF'20/'15, E2CDA'17
- National Science Foundation: CRI'15/'11, XPS'13, EAGER'11, CAREER'12
- Defense Advanced Research Projects Agency: PIPES'21, POSH'18, SDH'18, CRAFT'16, YFA'12
- Air Force Office of Scientific Research: YIP'15
- Semiconductor Research Corporation: JUMP'18, E2CDA'17
- Cornell College of Engineering: SPROUT'25
- NORDTECH Microelectronics Commons: C2S2 project team
- Intel Corporation: research funding and equipment donation
- Facebook: research funding
- NVIDIA: research funding and equipment donation
- Xilinx: research funding and CAD tool donation
- Cornell Engineering Learning Initiatives: undergraduate research funding
- Synopsys, Cadence, Mentor: CAD tool donation
- GitHub: hosted software donation
Professional Activities
- Conference PC Chair: IEEE Micro TopPicks'23
- Conference PC Member: ISCA'25/'22/'17/'15/'13, IEEE Micro TopPicks'22/'16, MICRO'20/'15
- Conference PC Member: SC'17/'16, HPCA'16, PPoPP'13, ASPLOS'11
- Conference External Reviewer: ISCA, ASPLOS, MICRO, HPCA, DAC, SIGMETRICS
- Conference Organizing Committee Member: HPCA'14
- Workshop PC Member: WDDD'16, GPGPU'16, NOPE'15, WDDD'15, GPGPU'14
- Workshop Co-Organizer: SIGARCH Visioning Workshop on Open and Agile HW Design, WARP'15, WINDS'10
- Tutorial Co-Organizer: PyMTL'19, PyMTL/Pydgin'15
- Associate Editor: IEEE Micro'20–23
- Journal Reviewer: IEEE Micro, CACM, JETCAS, TCAD, TVLSI, TACO, CAL, MICPRO, COMPUTER
- Book Reviewer: Morgan and Claypool Synthesis Lectures on Computer Architecture
- Member: IEEE Computer Society, ACM SIGARCH