Helena Caminal
hc922 [at] cornell.edu
Electrical and Computer Engineering Department
Cornell University

About Me

I am a final-year Ph.D. student in the Computer Systems Lab (CSL) at Cornell University, under the supervision of Professor José Martínez.

My PhD research is focused on the design of novel processing-using-memory architectures. Part of my work is based on rethinking classic concepts from associative processors (AP) from the 1970s to design RISC-V vector cores that deliver manifold speedups for a wide variety of applications. I've also worked on accelerating database analytics using APs and symbiotically redesigning parts of the database management system for AP.

From July 2015 to July 2017, I was a research assistant at the Barcelona Supercomputing Center working on the Riding on Moore's Law (RoMoL) European Project, lead by Professor Mateo Valero. My research focused on exploring how to improve energy efficiency using vector architectures. During that time, I also obtained a M.S. on High Performance Computing at Universitat Politècnica de Catalunya.

I obtained a B.S. and M.S. in Electrical Engineering from Universitat Politècnica de Catalunya in December 2014. I conducted my M.S. Thesis on 3D vision for swarm robotics at IRIDIA - CoDE laboratory at Université Libre de Bruxelles under the supervision of Professor Carlo Pinciroli.

I'm on the job market looking for an industry research or product position starting in the Spring 2023.

Publications and Inventions

Accelerating Database Analytical Query Workloads using an Associative Processor
H. Caminal*, Y. Chronis*, T. Wu, J. Patel, J. Martínez

CAPE: A Content-Addressable Processing Engine
H. Caminal, K. Yang, S. Srinivasa, A. Ramanathan, K. Al-Hawaj, T. Wu, V. Narayanan, C. Batten, J. Martínez

Content-Addressable Processing Engine
J. Martínez, H. Caminal, K. Yang, K. Al-Hawaj, C. Batten
U.S. Patent No. 11,461,097, issued October 4, 2022.

Semi-automatic validation of cycle-accurate simulation infrastructures: The case for gem5-x86
J. M. Cebrian, A. Barredo, H. Caminal, M. Moreto, M. Casas, M. Valero
Future Generation Computer Systems 2020

Using Arm’s scalable vector extension on stencil codes
A. Armejach, H. Caminal, J. M. Cebrian, R. Langarita, R. Gonzalez-Alberquilla, C. Adeniyi-Jones, M. Valero, M. Casas, M. Moreto
The Journal of Supercomputing 2020

Stencil codes on a vector length agnostic architecture
A. Armejach, H. Caminal, J. M. Cebrian, R. Gonzalez-Alberquilla, C. Adeniyi-Jones, M. Valero, M. Casas, M. Moreto

Performance and energy effects on task-based parallelized applications
H. Caminal, D. Caballero, J. M. Cebrian, R. Ferrer, M. Casas, M. Moreto, X. Martorell, M. Valero
The Journal of Supercomputing 2018

* Equally-contributing co-authors.

Experience, Fellowships and Other

Intern, Google Edge TPU Architecture, Mountain View, CA
May 2022 - August 2022

Research Intern, Micron Technology, Folsom, CA
February 2021 - May 2021

Jacobs Scholar Fellowship, Cornell University, 2017

Research Intern, Arm, Cambridge, UK
July 2016 - October 2016

Severo-Ochoa Fellowship, FIB, Universitat Politecnica de Catalunya
2015 - 2017

Research Intern, Barcelona Supercomputing Center, Spain
2015 - 2017

Intern, The Dataverse, Data Science at Harvard's Institute, Cambridge, MA
July 2014 - September 2014

Research Assistant, CITCEA-UPC, Barcelona, Spain
September 2012 - September 2013