Building prototype systems can be one of the best ways to validate assumptions, gain intuition about practical design issues, and provide platforms for future software research. While the research ideas behind these prototypes can be published in top-tier conferences, there are not many venues suitable for focusing on the actual prototype itself. At the same time, building an FPGA, ASIC, or full-custom computer architecture prototype is a non-trivial endeavor and requires a significant financial and time commitment. This workshop is intended as a forum for the builders in our community to share their practical on-the-ground experiences, to provide a status update on their progress, and to convey insights for those considering prototyping their ideas.

This half-day workshop was held on Sunday, June 14th, 2015, co-located with ISCA-42 in Portland, OR. The technical program committee and workshop organizers selected a particularly strong program from a record number of submissions. The 11 talks covered a broad range of exciting prototypes including: millimeter-scale full-system sensor motes and large-scale ASIC designs with 100's of millions of transistors; chip tapeouts in older technologies, chip tapeouts in a state-of-the-art 28nm process, and chip tapeouts using 3D integration; multicore chip tapeouts with heterogeneous accelerators; and FPGA prototypes focusing on multicore processors, network interfaces, and memory systems.

Participation was encouraged for anyone interested in learning about some of the best prototyping work going on within the computer architecture research community. Participation was also encouraged for researchers that have recently constructed or are currently constructing prototypes, for those considering embarking on a prototyping effort, or even for those who strongly disagree with the need to build prototypes. Ultimately, we had over 60 researchers from both academia and industry participate in the workshop.

Advance Program

12:301:30pm Lunch
1:301:34pm Welcoming Remarks
1:341:51pm Prototyping Heterogeneous System-on-Chip Architectures: A System-Level Design Approach
L. Carloni (Columbia University)
1:512:08pm From PDF to GDS: Designing the RoboBee SoC
B. Reagen, X. Zhang, D. Brooks, G.-Y. Wei (Harvard University)
2:082:25pm State of the Akvario Project
A. Hindborg, N. Jensen, P. Schleuniger, S. Karlsson (Technical University of Denmark)
2:252:35pm Break
2:352:52pm Designing a Complex 25-Core Academic Processor
D. Wentzlaff, M. McKeown, Y. Fu, T. Nguyen, Y. Zhou, J. Balkind, A. Lavrov, M. Shahrad, S. Payne (Princeton University)
2:523:09pm Post Mortem on Building 28nm/45nm RISC-V Vector Microprocessors with Chisel and the Rocket Chip Generator
Y. Lee, A. Waterman, R. Avizienis, H. Cook, C. Sun, B. Zimmer, K. Asanovic (University of California, Berkeley)
3:093:26pm Lessons from Five Years of Making Michigan Micro Motes
P. Pannuto, Y. Lee, Z. Foo, G. Kim, D. Blaauw, P. Dutta (University of Michigan)
3:304:00pm Coffee Break
4:004:17pm NVM-Charade: Open-Sourced FPGA-Based NVM Characterization Scheme
G. Park, M. Shihab, L. Nahar, W. Choi, D. Donofrio, J. Shalf, M. Jung (University of Texas at Dallas and Lawrence Berkeley National Laboratory)
4:174:34pm Experiences with Two FabScalar-Based Chips
E. Forbes, R. Chowdhury, B. Dwiel, A. Kannepalli, V. Srinivasan, Z. Zhang, R. Widialaksono, T. Belanger, S. Lipa, E. Rotenberg, W.R. Davis, P.D. Franzon (North Carolina State University)
4:344:51pm Experiences and Lessons from a 3D Integrated Prototype
R. Dreslinski (University of Michigan)
4:515:08pm A 10G NetFPGA Prototype for In-Network Aggregation
V.T. Lee, J. Nelson, M. Oskin, L. Ceze (University of Washington)
5:085:25pm Cymric: A Framework for Prototyping Near-Memory Architectures
C. Kersey, H. Kim, S. Yalamanchili (Georgia Institute of Technology)

(*) In order to encourage authors to present unpublished work-in-progress, we allowed authors to choose not to make their extended abstracts public. To learn more, please attend the workshop!



Workshop Archives