Workshop on Complexity-Effective Design

June 18, 2006
Boston, Massachusetts

To be held in conjunction with the 33rd International Symposium on Computer Architecture (ISCA-33)



Prior WCEDs

Panel Information
Title: An Agenda for Computer Architecture Research on Hardware Complexity
Moderator: Josep Torrellas, University of Illinois (Introduction, Conclusions)

David H. Albonesi
Cornell University

Pradip Bose
IBM T. J. Watson Research Center

Prabhakar Kudva
IBM T. J. Watson Research Center

Diana Marculescu
Carnegie-Mellon University

Motivation: The quest for higher performance via deep pipelining, speculative and multi-threaded execution, and chip-multiprocessing, has yielded microprocessors with greater performance, but at the expense of greater design complexity. The costs of higher complexity are many-fold, including increased verification time, higher power dissipation, and reduced scalability with microarchitectural resource size parameters and process shrinks. The goal of this workshop is to provide a forum for microarchitects, circuit designers, performance modelers, compiler developers, verification experts, and system designers to discuss and explore hardware/software techniques and tools for creating future designs that are more complexity-effective (CE).

Topics of interest:

Full conference length papers are fine but not a requirement. Short idea/position papers addressing one of the above issues are encouraged. We highly encourage "perspectives" or "real world experience" articles from industry.

Program Committee:

Submission deadline (extended abstract or full paper in PDF format emailed to any of the co-chairs): April 19, 2006
Acceptance notification: April 28, 2006
Final version due: May 19, 2006

A post-workshop proceedings, containing abstracts, full papers, and/or talk slides, will be distributed.