Tilera TILE64 Intra-Chip Mesh Network

D. Wentzlaff, P. Griffin, H. Hoffmann, L. Bao, B. Edwards, C. Ramey, M. Mattina, C.-C. Miao, J.F. Brown, and A. Agarwal. "On-Chip Interconnection Architecture of the Tile Processor." IEEE Micro, 27(5):15–31, September/October 2007.

This paper describes the mesh networks used in the Tilera TILE64 processor. This processor evolved from research done at MIT as part of the Raw tiled chip-multiprocessor project. Students might want to first read through the related TPDS'05 paper, which describes in more detail the dynamic and static networks used in the Raw processor. The TPDS'05 paper also introduces a new set of application requirements for so-called "scalar operand networks". Students should understand each of the five mesh networks used in the TILE64 processor. What is the routing and flow-control used on each network? How is deadlock-avoided in each network? What do students think about the authors' choice to use multiple physical networks as opposed to virtual channels? Students should spend some time on the later sections of the paper, since they discuss how software interacts with an on-chip interconnection network. The hardware-side demultiplexing and hardwall protection scheme are also interesting techniques for discussion.