Conducting future manycore architecture research will require new approaches to microarchitectural simulation, and there have been several proposals for FGPA-based execution-driven manycore simulators. This group explored how to efficiently build FPGA models of on-chip networks suitable for use in such simulators. They implemented a simple mesh network simulator in an FPGA as well as techniques to improve the simulator's area efficiency by time multiplexing router datapaths and buffer ports.

Application-aware routing uses static knowledge of an application's communication pattern to determine optimal or near-optimal routes offline. This group investigated various techniques for improving this routing algorithm's performance, flexibility, and robustness using a combination of analytical modeling and simulation.

Some foundries and CAD tools are now starting to support 45 degree diagonal wiring on certain metal layers. This group explored how to leverage this new technology in mesh-based networks with either short diagonal channels between neighboring routers or longer diagonal express channels.

System-on-chip designs often include a heterogeneous mix of processors, accelerators, and memories that communicate using an irregular set of point-to-point physical channels. This group first developed a technique based on simulated-annealing for floorplanning such designs so as to minimize the communication latencies of the point-to-point channels. They then investigated techniques to add on-chip network routers in an ad-hoc manner to more efficiently satisfy the desired bandwidth demands while balancing the channel and serialization latencies.

Nanophotonics is an emerging technology that can potentially improve the bandwidth density and energy efficiency of intra-chip and inter-chip interconnection networks. This group researched the inter-core network architecture implications of building multicore processors out of smaller chiplets interconnected via a nanophotonic hub chip. The hope is that nanophotonics can enable inter-chiplet communication to approach intra-chip communication in terms of latency, bandwidth density, and energy efficiency. If successful, this might move ASIC design towards chiplet composition as opposed to large-scale monolithic integration.

This group proposed "express networks" to reduce the zero-load latency in high-diameter on-chip mesh networks. An express network is a separate low-latency, low-bandwidth physical network that augments a base mesh network. Unlike multiple physical networks, an express network topology differs from the base network topology and is focused on reducing latency as opposed to increasing throughput. Unlike express channels, an express network includes separate express routers and provides connections between multiple mesh dimensions. This group evaluated a specific type of 4-ary tree express network for an 8-ary 2-dimensional on-chip mesh base network.