Globally Synchronized Frames for QoS in Intra-Chip Networks

J.W. Lee, M.C. Ng, and K. Asanović. "Globally Synchronized Frames for Guaranteed Quality-of-Service in On-Chip Networks." International Symposium on Computer Architecture (ISCA), June 2008.

This paper focuses on providing quality-of-service (QoS) guarantees for on-chip networks. So far in the course we have been focusing on performance, area, and energy, but QoS is another important requirement for many applications. Figure 2 is a good illustration of what we discussed in class: locally fair round-robin arbiters can produce a globally unfair bandwidth allocation. Adaptive routing algorithms help evenly distribute load across channels (as shown in Figure 2b) but does not ensure that this load is evenly distributed among flows. The age-based arbitration scheme discussed in Section 2.2 is essentially the FIFO-based arbitration we discussed in class where the timestamps are created when a packet is injected into the network. To understand the GSF technique, students should spend time working through the narrative in Section 3. Focus on how GSF approximates the idealized (zero-cycle network traversal and infinite priority queues) deadline-based arbitration. Students should feel free to skim through the detailed injection and window shifting algorithms and instead focus on the high-level mechanisms. Students should try and understand why the carpool lane sharing and early reclamation of empty frames can help improve performance. What assumptions does this technique make about the traffic pattern? When are the flows specified? Early reclamation depends on a global barrier network. Is this reasonable in the on-chip network context? Could we use such a global barrier network for other aspects of an interconnection network? Interested students may want to read the later MICRO'09 paper which discusses some of the disadvantages of GSF and proposes a different scheme called "preemptive virtual clocks".