Cornell University
School of Electrical and Computer Engineering
ECE 5970 Chip-Level Interconnection Networks
Spring 2010
Prof. Christopher Batten
207 Upson Hall • Tuesday and Thursday • 10:10–11:25am
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Simplifed Router Microarchitecture for Intra-Chip Networks
John Kim. "Low-Cost Router Microarchitecture." International Symposium on Microarchitecture (MICRO), December 2009.
- Discussion: March 16 shepherded by Daniel Lo
- Online Copy: kim-router-uarch-micro2009.pdf (link)
This paper presents a greatly simplified router microarchitecture suitable for on-chip 2D mesh networks that use dimension-ordered routing. Students should be able to understand all aspects of this paper. Pay particular attention to the implementation details for handling arbitration, flow control, and starvation. How can such a simplified design achieve competitive results with the baseline architecture shown in Figure 10? How does this baseline architecture compare to highly-speculative state-of-the-art virtual-channel router microarchitectures in terms of performance and design complexity? Compare the general approach taken in this paper with the ISCA'04 paper by Mullins et al.