Flattened Butterfly Topology for Intra-Chip Networks

J. Kim, J. Balfour, and W.J. Dally. "Flattened Butterfly Topology for On-Chip Networks." International Symposium on Microarchitecture (MICRO), December 2007.

This more recent paper proposes a new approach based on flattening the "rows" in a standard butterfly topology. Students might want to skim the beginning of the ISCA'07 paper for more background on this topology (particularly Figure 1). Focus on understanding why flattening is advantageous, and why this paper appears to contradict the earlier TOC'90 paper. The TOC'90 paper argues for low-dimensional networks with low-radix switches, while the MICRO'07 paper argues for a flattened butterfly specifically because it has high-radix switches. Although we have not discussed routing algorithms in detail, students should still spend some time trying to understand the simple routing algorithm described in Section 3.2. While it is important to understand the motivation behind the router bypass channels, students new to interconnection networks should not spend too much time on the router microarchitecture details in 4.1–4.4. Although we have not talked too much about virtual channels, students should still read Section 6.4 since Figure 14 actually does a good job of illustrating how virtual channels work. What do students think about the evaluation methodology? What about the scaling story? If the flattened butterfly topology has lower power, higher throughput, and lower latency compared to mesh topologies, are there any reasons an architect might still choose a mesh topology?