SCARAB Intra-Chip Network

M. Hayenga, N.E. Jerger, and M. Lipasti. "SCARAB: A Single-Cycle Adaptive Routing and Bufferless Network." International Symposium on Microarchitecture (MICRO), December 2009.

We have mentioned several times in class that on-chip networks have different resource constraints as compared to inter-chip networks: wiring resources are usually more abundant, while buffering resources are usually more expensive. A logical research direction is to explore bufferless on-chip networks. Note that such networks still include "buffers"; the term "bufferless" refers to bufferless flow-control. In other words, packets are not buffered when there is contention in the network. The related ISCA'09 paper by Moscibroda et al. uses deflection routing (also called hot-potato routing) and is similar to the CHAOS adaptive routing algorithm we discussed earlier. Students should try and understand the disadvantages of this earlier work and how the primary MICRO'09 paper attempts to address these issues. The proposed SCARAB architecture is quite different from many of the architectures we have studied so far, so it might take some time for students to work their way through the paper. SCARAB actually includes three different networks: an allocation network, a data network, and a nack network. Students should understand why three networks are necessary and what routing and flow-control is used for each. How do the networks inter-operate? Students with less computer architecture background might want to skip the section on opportunistic buffering, although those with more background will find it very interesting. The authors only compare their proposed network architecture to other bufferless approaches. Students might want to skim the related ISCA'09 paper, which compares a bufferless architecture based on deflection routing to other buffered flow-control schemes.