Hierarchical Topologies for Intra-Chip Networks

R. Das, S. Eachempati, A.K. Mishra, V. Narayanan, and C.R. Das. "Design and Evaluation of a Hierarchical On-Chip Interconnect for Next-Generation CMPs." International Symposium on High-Performance Computer Architecture (HPCA), February 2009.

This paper proposes a practical hybrid topology with a local bus network interconnected by a global mesh network. Students should spend some time understanding Figure 2a and Figure 10 in an effort to begin building intuition on the power consumption of on-chip networks. Students new to interconnection networks should understand the main idea behind the XShare technique but should not be overwhelmed by the detailed implementation issues discussed in Sections 3.4–3.5. How do students feel about the communication locality assumption? Try and verify how the authors derive the channel widths in Figure 6a. What exactly are the authors normalizing? What would the flattened butterfly 16-node and 256-node topologies look like? How faithfully do the authors reproduce the flattened butterfly network described in the MICRO'07 paper? What are the implications of the processor, cache, and memory controller placement in Figure 6b? What is the authors' rationalization for advocating a network which has significantly lower saturation throughput as compared to the other topologies in Figure 7? Students may want to skim through the NOCS'09 paper and compare the hybrid topology with the more general concept of "external concentration". How does Figure 1d of the NOCS'09 paper compare to Figure 1c of the HPCA'09 paper?