Design-Space Exploration for Intra-Chip Networks

J. Balfour and W.J. Dally. "Design Tradeoffs for Tiled CMP On-Chip Networks." International Symposium on Supercomputing (ICS), June 2006.

This paper compares the performance, area, and energy of various network architectures for an on-chip interconnection network. Sections 2.2 and 4 provide a first-order model for evaluating the area and energy of an on-chip network architecture. Some of these models may be of use to students for their final project, so students are encouraged to work their way through the equations. Section 5 provides an overview of the five network architectures under consideration and discusses the topology, routing, and flow-control used in that architecture. This section is an excellent example of how to apply many of the concepts we discussed in the first part of the course. Pay special attention to the type of routing algorithm used in each architecture and the implications on the number of virtual channels necessary to avoid deadlock. Students should be able to derive all of the numbers in Table 3. Why do the authors cite the Duato TPDS'93 paper when discussing the oblivious O1TURN routing algorithm used for the mesh topologies? What do students think about the closed-loop evaluation methodology? Overall, students should be able to understand all of Sections 5–7, and hopefully the early sections will start to build intuition about the area and energy cost of on-chip networks.