- Developed a RTL implementation of flexible associative cache (using way-prediction) which provides performance similar to set associative cache but energy consumption similar to direct-mapped cache.
- Performed detail analysis of energy consumption of each component of the baseline FSM cache to guide the cache design.
- Developed cycle-level C models of set-associative and way-prediction caches to analyze their performance on SPEC2000 benchmarks and guide RTL design decisions like predictor table size & bits used for hashing.
- Designed and implemented the way prediction cache, that accesses only one entry from data-array at the speculated way obtained from a predictor table, in Verilog.
- Demonstrated 28% energy savings at cost of only performance loss compared to set-associative cache.
Design of Flexible Associative Cache based on Way Prediction
Neeraj Kulkarni
Ph.D candidate, Computer Systems Laboratory
My research interests include high-performance computer architecture, datacenters, system resource management.