Power Management in Heterogeneous Reconfigurable Multi-Core Architectures

  • Built an energy-efficient multicore system to tackle the dark silicon problem using asymetric & reconfigurable CPU cores that operate by turning on/off lanes in sections of the superscalar out-of-order pipeline.
  • Formulated it as an optimization problem that involves mapping applications onto different core types & reconfiguringthe cores, to maximize the system throughput while operating under a power budget.
  • Developed techniques to tackle the challenging combined problem of thread-to-core mapping & core reconfiguration in just a few milliseconds using machine learning and global optimization algorithms.
  • Our approach outperforms prior work, namely core-level gating and Flicker (technique aimed at homogeneous reconfigurable multicores) by up to 30% and 15% respectively.
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Neeraj Kulkarni
Ph.D candidate, Computer Systems Laboratory

My research interests include high-performance computer architecture, datacenters, system resource management.