IBM Cell Intra-Chip Ring Network

T.W. Ainsworth and T.M. Pinkston. "Characterizing the CELL EIB On-Chip Network." IEEE Micro, 27(5):6–14, September/October 2007.

This paper provides a good description of the on-chip network used in the Cell processor, and provides some rough high-level estimates on the latency and throughput of this network. Students should focus on the additional mechanisms required to build a real on-chip network in practice. Try and understand all of the steps involved in sending a message between two of the SPEs. Many papers we have read focus just on the network itself; how much overhead does this paper suggest is involved in simply getting the message in and out of the network? The Cell on-chip network is actually three separate networks: the command tree-based network, the data global arbitration network, and the data ring network. What routing algorithm is used in the data ring networks? Ultimately what limits the latency and throughput of sending a message on the data ring network? Students interested in learning more about the Cell processor should skim through the related IBMJRD'05 paper.