Miscellaneous Handouts

• Course Syllabus
• Next Steps after First Lecture
• Tiny RISC-V Instruction Set Specification
• Verilog RTL Usage Rules
• Lab Assignment Logistics
• ECE 5740 Postion Paper Logistics

Lecture Handouts

• Course Overview (results from activities)
• T01: Processor Concepts (problems)
• T02: Processor Microarchitecture (problems)
• T03: Memory Concepts (problems)
• T04: Memory Microarchitecture (problems)
• T05: Integrating Processors and Memories (problems)
• T06: Advanced Processors – Superscalar Execution (problems)
• T07: Advanced Processors – Out-of-Order Execution (problems, I2OE, I2OL, IO2E)
• T08: Advanced Processors – Register Renaming (problems)
• T09: Advanced Processors – Memory Disambiguation (problems)
• T10: Advanced Processors – Branch Prediction (problems)
• T11: Advanced Processors – Speculative Execution (problems, extra)
• Extra Topic 1: VLIW Processors (extra)
• Extra Topic 2: SIMD Processors
• Extra Topic 3: Multithreaded Processors

Quiz Handouts

• Quiz 1: Overview (solution)
• Quiz 2: Instruction Set Architecture (solution)
• Quiz 3: FSM Processors (solution)
• Quiz 4: Pipelining - Data Hazards (solution)
• Quiz 5: Pipelining - Control Hazards (solution)
• Quiz 6: Direct Mapped vs. Fully Associative Cache (solution)
• Quiz 7: Integrating Processors and Memory (solution)
• Quiz 8: Superscalar Execution (solution)
• Quiz 9: Register Renaming (solution)
• Quiz 10: Out-of-Order Processors and L1 Data Cache (solution)

Section Handouts

• Section 1: Linux Development Environment (github)
• Section 2: RTL Design with Verilog (github)
• Section 3: RTL Testing with Python (github)
• Section 4: Lab 2 Head Start (github)
• Section 5: Pipelining Diagram Common Mistakes
• Section 5: Bug Hunt (github)
• Section 6: Problem-Based Learning (sol)
• Section 7: Open-Source Hardware (openroad,activity)
• Section 8: Lab 3 Head Start (github)
• Section 9: Memory Random Testing and Queues (github)
• Section 10: Problem-Based Learning (sol)
• Section 11: Lab 4 Head Start (github)
• Section 12: Networks (github)
• Section 13: Example Architecture – Intel Golden Cove

Lab Handouts

• Lab 1: Iterative Integer Multiplier (dpath, ctrl)
• Lab 2: Pipelined Processor (dpath)
• Lab 3: Blocking Cache (dpath, ctrl)
• Lab 4: Single-Core and Multi-Core Systems (results)

Tutorial Handouts

• Tutorial 0: Remote Access to ecelinux
• Tutorial 1: Linux Development Environment
• Tutorial 2: Git Distributed Version Control System (github)
• Tutorial 3: Verilog Hardware Description Language (github)