image/svg+xml
CacheNet
MCoreDataCache
proc req[0]
proc req[1]
proc req[2]
proc req[3]
proc resp[0]
proc resp[1]
proc resp[2]
proc resp[3]
Test Memory
port 0
mainmemreq
mainmemresp
MemNet
Bank
Bank
Bank
Bank
src
sink
src
sink
src
sink
src
sink
procreq/resp[0]
procreq/resp[1]
procreq/resp[2]
procreq/resp[3]
cachereq/resp
cachereq/resp
cachereq/resp
cachereq/resp
memreq/resp
memreq/resp
memreq/resp
memreq/resp
cachereq/resp[0]
cachereq/resp[1]
cachereq/resp[2]
cachereq/resp[3]
memreq/resp[0]
memreq/resp[1]
memreq/resp[2]
memreq/resp[3]
mainmem req/resp[0]
x
x
x