image/svg+xml
procreq/resp[0]
Test Memory
port 1
McoreDataCache
mainmem req/resp
MemNet
ICache
ICache
ICache
ICache
cachereq/resp
cachereq/resp
cachereq/resp
cachereq/resp
memreq/resp[0]
memreq/resp[1]
memreq/resp[2]
memreq/resp[3]
mainmem req/resp[0]
procreq/resp[1]
procreq/resp[2]
procreq/resp[3]
port 0
Proc #2
dmemreq/resp
imemreq/resp
Proc #3
dmemreq/resp
imemreq/resp
memreq/resp
memreq/resp
memreq/resp
memreq/resp
imemreq
imemresp
dmemreq
dmemresp
MultiCore
src
sink
src
sink
src
sink
src
Proc #0
dmemreq/resp
imemreq/resp
dmemreq/resp
Proc #1
imemreq/resp
sink