Cornell University
School of Electrical and Computer Engineering
ECE 2300 / ENGRD 2300
Digital Logic and Computer Organization
Fall 2025
Prof. Christopher Batten
Tue/Thu @ 11:40–12:55pm • 155 Olin Hall
home | syllabus | staff | schedule | handouts | readings | resources
Schedule Links
- Weekly schedule (times and locations for lecture, labs, office hours, discussion sections)
- Staffing schedule (who is staffing which lab, office hours, discussion sections)
- Semester schedule (in calendar format)
Semester Schedule in List Format
| Tue | Aug 26 | Lecture | Course Overview |
| Thu | Aug 28 | Lecture | Topic 1: Digital Circuits |
| Fri | Aug 29 | Section | Linux Development Environment |
| Tue | Sep 2 | Lecture | Topic 2: Combinational Logic |
| Thu | Sep 4 | Lecture | — Topic 2: Continued |
| Fri | Sep 5 | Section | Verilog Combinational Gate-Level Design |
| Tue | Sep 9 | Lecture | Topic 3: Boolean Algebra |
| Thu | Sep 11 | Lecture | — Topic 3: Continued |
| Thu | Sep 11 | Due | Lab 1, Part A |
| Fri | Sep 12 | Section | Verilog Testing |
| Tue | Sep 16 | Lecture | Topic 4: Combinational Building Blocks |
| Thu | Sep 18 | Lecture | — Topic 4: Continued |
| Thu | Sep 18 | Due | Lab 1, Part B |
| Due | Lab 1, Part D (report due three days after lab section) | ||
| Fri | Sep 19 | Section | Lab 2 Head Start |
| Tue | Sep 23 | Lecture | Topic 5: Number Systems |
| Thu | Sep 25 | Lecture | Topic 6: Sequential Logic |
| Thu | Sep 25 | Due | Lab 2, Part A |
| Fri | Sep 26 | Section | Verilog Combinational RTL Design |
| Tue | Sep 30 | Lecture | — Topic 6: Continued |
| Thu | Oct 2 | Lecture | Topic 7: Finite-State Machines |
| Thu | Oct 2 | Due | Lab 2, Part B |
| Due | Lab 2, Part D (report due three days after lab section) | ||
| Fri | Oct 3 | Section | Lab 3 Head Start |
| Tue | Oct 7 | Lecture | — Topic 7: Continued |
| Tue | Oct 7 | Exam | Prelim Exam 1 @ 7:30–9:00pm in 110 & B14 Hollister Hall |
| Thu | Oct 9 | Lecture | Topic 8: Sequential Building Blocks |
| Fri | Oct 10 | No Section | |
| Tue | Oct 14 | Fall Break – No Lecture | |
| Thu | Oct 16 | Lecture | — Topic 8: Continued |
| Thu | Oct 16 | Due | Lab 3, Part A |
| Fri | Oct 17 | Section | Verilog Memory Arrays |
| Tue | Oct 21 | Lecture | Topic 9: Instruction Set Architecture |
| Thu | Oct 23 | Lecture | — Topic 9: Continued |
| Thu | Oct 23 | Due | Lab 3, Part B |
| Fri | Oct 24 | Processor ISA Simulator | |
| Tue | Oct 28 | Lecture | Topic 10: Single-Cycle Processor |
| Thu | Oct 30 | Lecture | — Topic 10: Continued |
| Due | Lab 3, Part D (report due three days after lab section) | ||
| Fri | Oct 31 | Section | Problem-Based Learning |
| Tue | Nov 4 | Lecture | Topic 11: Multi-Cycle Processor |
| Tue | Nov 4 | Exam | Prelim Exam 2 @ 7:30–9:00pm in 101 & 219 Phillips Hall |
| Thu | Nov 6 | Lecture | — Topic 11: Continued |
| Thu | Nov 6 | Due | Lab 4, Part A |
| Fri | Nov 7 | Problem-Based Learning | |
| Tue | Nov 11 | Lecture | Topic 12: Pipelined Processor |
| Thu | Nov 13 | Lecture | — Topic 12: Continued |
| Thu | Nov 13 | Due | Lab 4, Part B |
| Fri | Nov 14 | Section | Problem-Based Learning |
| Tue | Nov 18 | Lecture | — Topic 12: Continued |
| Thu | Nov 20 | Lecture | Topic 13: Caches |
| Fri | Nov 21 | Exam | Verilog Exam @ Discusion Section Time Slot in 225 Upson Hall |
| Tue | Nov 25 | Lecture | — Topic 13: Continued |
| Tue | Nov 25 | Due | Lab 4, Part C |
| Thu | Nov 27 | Thanksgiving Break – No Lecture | |
| Fri | Nov 28 | Thanksgiving Break – No Section | |
| Tue | Dec 2 | Lecture | — Topic 13: Continued |
| Thu | Dec 4 | Lecture | Topic 14: Integrating Processors and Caches |
| Thu | Dec 4 | Due | Lab 4, Part E |
| Fri | Dec 5 | Section | TBD |
| Mon | Dec 8 | Due | Lab 4, Part G |
| TBD | Exam | Final Exam (location TBD) |