PhD Candidate in Electrical Engineering
Office: 365 Upson Hall, Ithaca, NY 14853
Phone: (607) 255-1456
Email: rz252 -at- cornell.edu
I am a PhD student at the School of Electrical and Computer Engineering at Cornell University supervised by Professor Zhiru Zhang. I am broadly interested in design automation, High-Level Synthesis, and code optimization for specialized architectures.
I obtained my BS in Electrical and Computer Engineering from the University of Toronto in 2014. During my undergrad I interned for Altera for 16 months in 2013, and at IBM for 4 months in 2014.
- R. Zhao, W. Song, W. Zhang, T. Xing, J. Lin, M. Srivastava, R. Gupta, and Z. Zhang. Accelerating Binarized Convolutional Neural Networks with Software-Programmable FPGAs Int'l Symp. on Field-Programmable Gate Arrays (FPGA), Feb 2017
- C. Xu, G. Liu, R. Zhao, S. Yang, G. Luo, and Z. Zhang. A Parallel Bandit-Based Approach for Autotuning FPGA Compilation Int'l Symp. on Field-Programmable Gate Arrays (FPGA), Feb 2017
- S. Dai, R. Zhao, G. Liu, S. Srinath, U. Gupta, C. Batten, and Z. Zhang. Dynamic Hazard Resolution for Pipelining Irregular Loops in High-Level Synthesis Int'l Symp. on Field-Programmable Gate Arrays (FPGA), Feb 2017
- R. Zhao, G. Liu, S. Srinath, C. Batten, and Z. Zhang. Improving High-Level Synthesis with Decoupled Data Structure Optimization Design Automation Conference (DAC), June 2016
- M. Tan, G. Liu, R. Zhao, S. Dai, and Z. Zhang. ElasticFlow: A Complexity-Effective Approach for Pipelining Irregular Loop Nests. Int'l Conf. on Computer-Aided Design (ICCAD), Nov. 2015
- R. Zhao, M. Tan, S. Dai, and Z. Zhang. Area-Efficient Pipelining for FPGA-Targeted High-Level Synthesis. Design Automation Conference (DAC), June 2015
Honours and Awards
- Cornell Graduate Fellowship, 2014
- Engineering Science Foundation Scholarship, 2011
- NSERC Undergraduate Student Research Award, 2011