Acceleration of Critical sections in Multi-Threaded Programs (Master's Thesis, IIT Kanpur)

  • Demonstrated that load/stores are majorly responsible for stalls in critical sections of multithreaded programs.
  • Proposed to accelerate critical section load/store requests by prioritizing them in Network-On-Chip switches in order to reduce the network buffer latency of critical requests & subsequently stall times of critical load/stores.
  • Developed algorithms to prioritize different categories of messages injected into the network at each NoC switch.
  • Evaluated our proposal on 128-core system using SPLASH2x, PARSEC and modified version of STAMP benchmark suites.
  • Achieved performance gain of upto 13% over a baseline system following round-robin/FIFO scheduling in the switches.
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Neeraj Kulkarni
Ph.D candidate, Computer Systems Laboratory

My research interests include high-performance computer architecture, datacenters, system resource management.